Multiphase Clock Correction with Independent Skew and Duty Control
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Solution Overview
Problem
Existing clock correction methods for multiphase clocks face challenges in performing skew adjustment without being affected by duty correction, leading to phase shifts and deteriorated jitter tolerance, especially in high-speed communication systems like PON, where precise timing is critical.
Innovation Solution
A clock correction device and method that performs skew adjustment under analog control using a phase difference between an output and reference clock, while separately managing duty correction through digital control, utilizing a correction circuit with a skew detection circuit, integration circuit, and comparator to generate adjustment signals, allowing for independent correction of skew and duty without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If digital correction is used for both skew adjustment and duty correction, then duty correction can be performed, but phase shift occurs again when duty correction is performed after skew adjustment
Solution Approach 1:
The correction device is divided into two independent correction circuits: a first correction circuit for skew adjustment and a second correction circuit for duty correction. This segmentation allows each circuit to perform its specific function without interfering with the other, preventing phase shift from occurring again after skew adjustment
Solution Approach 2:
The second correction circuit acts as an intermediary that performs duty correction on the output clock from the first correction circuit without affecting the skew adjustment already made. This intermediary structure enables duty correction while maintaining the stability of the previously adjusted phase relationship
2Manufacturing precision
If skew adjustment is performed during multiphase clock generation, then skew can be corrected at the source, but phase shift caused in the multiphase clocks cannot be corrected
Solution Approach 1:
The system is segmented into a clock generation unit that performs skew adjustment and a separate correction device that performs duty correction. This segmentation enables the correction device to handle phase shift issues in multiphase clocks without affecting the original skew adjustment functionality
Solution Approach 2:
The correction device operates in a different dimension (duty cycle domain) rather than trying to modify the phase domain adjustments already made. By correcting duty cycle separately, the system can address phase shift issues without undoing the skew adjustment performed during clock generation
3Speed
If high-speed multiphase clocks are distributed using a clock distribution circuit, then communication speed increases, but phase shift among clocks occurs due to bandwidth insufficiency
Solution Approach 1:
The correction device uses feedback mechanisms to detect and correct phase shifts in distributed multiphase clocks. By continuously monitoring the clock signals and adjusting duty cycles based on detected deviations, the system maintains clock phase accuracy even at high communication speeds
Solution Approach 2:
The correction device changes the duty cycle parameter of the distributed clocks to compensate for phase shifts caused by bandwidth limitations in the clock distribution circuit. This parameter adjustment allows high-speed operation while maintaining timing accuracy
Data Source
AI summary
A clock correction device performs skew adjustment and duty correction of an input clock concurrently or in parallel. The clock correction device includes a correction circuit that performs skew adjustment of an input clock by analog control using a skew adjustment signal based on a phase difference between an output clock and a reference clock, receives a duty control signal, and performs duty correction of the input clock by digital control, a skew detection circuit that receives inputs of the output clock and the reference clock and, when only the reference clock is in a predetermined state, outputs a detection signal that changes to the predetermined state, an integration circuit that integrates the detection signal and generates a first voltage signal, and a comparator that compares the first voltage signal and a first reference signal to thereby generate the skew adjustment signal.


