Multi-Phase Clock Calibration Using Gated Time-Difference Measurement
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Solution Overview
Problem
Current multi-phase clock calibration techniques face challenges due to phase differences between the final output and reference phase differences in clock circuits, leading to errors, and existing methods like adjusting the control voltage of voltage-controlled oscillators (VCO) or phase-locked loop (PLL) delays are costly and power-intensive.
Innovation Solution
A calibration method and device that gate multi-phase clock signals as primary and auxiliary signals with predetermined phase differences, calculate time differences, determine delay adjustment amounts, and obtain phase errors to achieve calibration, using a selector and time difference obtaining module to adjust delays without additional reference sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the control voltage of voltage-controlled oscillators (VCO) or phase-locked loop (PLL) delays is adjusted for calibration, then phase calibration accuracy is improved, but hardware cost and power consumption increase
Solution Approach 1:
The patent extracts the calibration function from complex VCO/PLL control mechanisms and implements it through a dedicated calibration device that uses simple gating operations and time difference measurements. This separates the calibration functionality from the main clock generation path, achieving accurate phase calibration without the power-intensive VCO control voltage adjustment.
Solution Approach 2:
The patent creates auxiliary clock signals as copies of the original multi-phase clock signals through gating operations. By comparing the original signals with these copied auxiliary signals, the system can measure time differences and calculate phase errors without directly manipulating the high-power VCO control voltages, thereby reducing power consumption while maintaining calibration accuracy.
2Measurement precision
If the control voltage of voltage-controlled oscillators (VCO) or phase-locked loop (PLL) delays is adjusted for calibration, then phase calibration accuracy is improved, but hardware cost increases
Solution Approach 1:
The patent extracts the calibration function from complex VCO/PLL control mechanisms and implements it through a dedicated calibration device that uses simple gating operations and time difference measurements. This separates the calibration functionality from the main clock generation path, achieving accurate phase calibration without the power-intensive VCO control voltage adjustment.
Solution Approach 2:
The patent creates auxiliary clock signals as copies of the original multi-phase clock signals through gating operations. By comparing the original signals with these copied auxiliary signals, the system can measure time differences and calculate phase errors without directly manipulating the high-power VCO control voltages, thereby reducing power consumption while maintaining calibration accuracy.
3Manufacturing precision
If multi-phase clock signals are gated with predetermined phase differences and time differences are calculated, then calibration accuracy is improved, but measurement and detection difficulty increases
Solution Approach 1:
The patent applies preliminary gating operations to the multi-phase clock signals to create auxiliary signals with predetermined phase differences before measurement. This preliminary action prepares the signals in advance, establishing known reference relationships that simplify the subsequent time difference measurement and calculation processes, thereby improving calibration accuracy while managing measurement complexity.
Data Source
AI summary
The application provides a calibration method, a calibration device and a multi-phase clock circuit. The method includes: gating each of multi-phase clock signals as a first primary clock signal and gating a corresponding clock signal as a first auxiliary clock signal according to a first preset rule; gating each of the multi-phase clock signals as a second primary clock signal and gating a corresponding clock signal as a second auxiliary clock signal according to a second preset rule; obtaining a time difference between each primary clock signal and its corresponding auxiliary clock signal under the first preset rule and the second preset rule; determining a delay adjustment amount of each primary clock signal according to the time difference, and obtaining a phase error between the multi-phase clock signals according to the delay adjustment amount; and obtaining a calibration amount of the multi-phase clock signals according to the phase error.