Multi-Phase Clock Buffer Circuit for High-Speed Timing Margin
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Solution Overview
Problem
Conventional multi-phase clock generation circuits for semiconductor memory devices using D flip-flops and inverters fail to ensure sufficient margin for high-speed operation due to internal time delays, leading to improper data input/output timing.
Innovation Solution
A multi-phase clock generation circuit with a first and second clock buffer unit that inverts and buffers internal clocks in synchronization with edges of an external clock, generating internal clocks with phase differences of 90°, 180°, and 270°, thereby ensuring equal periods and reducing internal time delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If D flip-flops and inverters are used to generate multi-phase internal clocks, then the circuit can generate multiple phases, but internal time delays propagate through the components causing insufficient margin for high-speed operation
Solution Approach 1:
The patent inverts the conventional approach by using buffer units that are driven by the external clock signal to generate internal clocks, rather than using D flip-flops that propagate signals through multiple stages. This inversion eliminates the cumulative time delays associated with cascaded flip-flop and inverter stages, providing sufficient timing margin for high-speed operation.
2Manufacturing precision
If multiple D flip-flops and inverters are used to generate internal clocks with 90° phase differences, then the required phase distribution is achieved, but the internal time delay prevents proper data input/output timing
Solution Approach 1:
The patent extracts the clock buffering function from the data path by using dedicated buffer units driven directly by the external clock. This separation removes the time-delaying elements (D flip-flops and inverters) from the critical data input/output path, eliminating internal time delays while maintaining precise phase differences through the buffer synchronization mechanism.
3Device complexity
If conventional clock generation methods are used, then the circuit structure is simple, but the internal time delay propagates through D flip-flops and inverters preventing normal operation
Solution Approach 1:
The patent introduces buffer units as intermediary components between the external clock and the internal clock generation stages. These buffer units act as mediators that synchronize the clock signals without introducing the cumulative delays associated with D flip-flop and inverter chains, thereby enabling normal high-speed data input/output operation while maintaining a relatively simple circuit structure.
Data Source
AI summary
A multi-phase clock generation circuit includes a first clock buffer unit configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock, and a second clock buffer unit configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock.