Multiphase Clock Generation Using VCO and Johnson Counters
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Solution Overview
Problem
Existing methods for generating multiple-phase clock signals face challenges such as asymmetric waveforms due to mismatched parasitic capacitances, increased circuit complexity, and phase errors from interpolation techniques, which limit frequency operation and require extensive circuitry.
Innovation Solution
A system comprising a multiple-stage voltage controlled oscillator (VCO) operating at a frequency N times higher than the required output, generating M equally spaced outputs with different phases, which are then divided by a clock divider circuit using modified Johnson counters to produce M×N equally spaced clock pulses with the same frequency and accurate phase differences, enabled by sequential logic to maintain output sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ring oscillator with multiple stages is used to generate multiphase clock signals, then multiple clock phases can be generated, but the circuit layout must be absolutely matched and parasitic capacitances must be identical, which increases device complexity and is difficult to manufacture
Solution Approach 1:
The patent divides the clock generation function into two independent segments: a ring oscillator that generates clock signals and a separate delay circuit that creates phase differences. This segmentation allows each component to be optimized independently, eliminating the need for absolute layout matching between multiple oscillator stages while still achieving accurate multiphase clock generation.
2Adaptability or versatility
If the number of stages in a ring oscillator is increased to generate more clock phases, then more clock phases are available, but parasitic loading in intermediate nodes increases which limits the frequency of operation
Solution Approach 1:
The patent introduces a delay circuit as an intermediary component between the ring oscillator and the output. This delay circuit generates the required phase differences without requiring additional oscillator stages, thereby maintaining high operating frequency while providing the necessary number of clock phases.
3Adaptability or versatility
If interpolation techniques are used to generate multiple phase clock signals, then clock phases can be generated, but phase errors occur and large deviations result from mismatch during the interpolation process
Solution Approach 1:
The patent uses a ring oscillator to generate base clock signals that are then copied and delayed to create multiple phases. This approach avoids the interpolation process entirely, eliminating phase errors and mismatches that occur when dividing or interpolating clock phases, while maintaining accurate phase relationships.
4Adaptability or versatility
If a multiple-stage voltage controlled oscillator with Johnson counters and shift registers is used to generate multiple phase clock signals, then multiple clock phases can be generated, but the circuitry required is very large and extensive
Solution Approach 1:
The patent combines the delay function and phase generation into a single integrated delay circuit that works with the ring oscillator. This merged design eliminates the need for separate Johnson counters and multiple shift registers, significantly reducing circuit complexity while maintaining the ability to generate multiple accurate clock phases.
Data Source
AI summary
A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.