Multi-Phase Spread Spectrum Clocking for PLL EMI Reduction
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Solution Overview
Problem
Conventional Phase Lock Loops (PLLs) generate clock signals with concentrated power, leading to electromagnetic interference that exceeds regulatory limits, such as EN55015, FCC PART 18, and JIS, affecting other electronic devices.
Innovation Solution
A Spread Spectrum Clock Generator (SSCG) that employs a Phase/Frequency Detector, Voltage Control Oscillator, multiplexer, and pattern generator to spread the frequency of clock signals, reducing average power and minimizing interference by distributing the signal energy across multiple phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional PLL generates clock signals with concentrated power, then the signal strength is sufficient, but electromagnetic interference exceeds regulatory limits
Solution Approach 1:
The patent segments the concentrated clock signal into multiple phase-shifted copies (typically 2-8 copies with phase differences of 180 degrees or less). By distributing the signal power across multiple phases rather than concentrating it in a single frequency, the peak power spectral density is reduced while maintaining sufficient signal strength, thereby resolving the contradiction between signal strength and electromagnetic interference
Solution Approach 2:
The patent dynamically adjusts the phase relationships between multiple clock signal copies using phase shifters and multiplexers. The system dynamically combines these phase-shifted signals to create a spread spectrum clock signal that maintains adequate strength while distributing power across a wider frequency range, reducing electromagnetic interference to comply with regulatory limits
2Power
If clock signal power is concentrated at a single frequency, then signal strength is maximized, but interference with other electronic devices occurs
Solution Approach 1:
The patent segments the single-frequency clock signal into multiple phase-shifted frequency components. By distributing the total signal power across multiple frequencies (f0, f1, f2, etc.) rather than concentrating it at one frequency, the peak power at any single frequency is reduced, minimizing interference with other electronic devices while maintaining overall signal strength through the combined energy of all phases
Solution Approach 2:
The patent changes the frequency domain parameters of the clock signal by introducing phase shifts and combining multiple frequency components. This parameter transformation converts a concentrated single-frequency signal into a spread spectrum signal with distributed power across multiple frequencies, thereby reducing interference with other devices while preserving signal integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SSCG effectively reduces the average power of clock signals, preventing interference with other electronic devices and ensuring compliance with regulatory standards by spreading the signal energy across multiple phases, thereby controlling the output frequency.
Implementation Method 1
a Voltage Control Oscillator (VCO) coupled to the output end of the voltage controller for outputting a plurality of clock signals; wherein the plurality of the clock signals have a same frequency according to the voltage output from the voltage controller; wherein phases of the plurality of the clock signals are different to each other
Data Source
AI summary
A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. The clock signals of different phases are selectively fed back to the phase frequency detector. In this way, the frequency of the output signal is changed, which achieves spreading spectrum.


