Multi-Phase Clocking for Low-Ripple Signal Transmission

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Solution Overview

Problem

Conventional signal transmitting systems experience power ripples due to synchronized operation clock signals, leading to system noise and operational issues.

Innovation Solution

Implementing a multi-phase clock signal generating circuit to generate operation clock signals with different phases for various transmitting circuits, ensuring that logic level transitions do not occur simultaneously across the system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all transmitting circuits use the same phase operation clock signal, then the system operation is simple and synchronized, but power ripples occur due to simultaneous logic level transitions

Engineering Contradiction:
Improvesystem stabilityVSAvoidpower ripple
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the single-phase clock signal into multiple phase clock signals (first phase clock signal, second phase clock signal, etc.) that are distributed to different transmitting circuits. This segmentation causes logic level transitions to occur at different times across circuits, thereby reducing power ripples while maintaining systematic operation.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If operation clock signals have the same phase, then circuit synchronization is easy to implement, but signal noise increases due to power ripples

Engineering Contradiction:
Improveclock signal generationVSAvoidsignal noise
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent implements periodic action by generating multiple phase clock signals with different phases (e.g., 0°, 120°, 240° for three phases) that periodically cycle through different transmitting circuits. This periodic phase distribution ensures that logic transitions are spread out in time, reducing signal noise while maintaining regular, predictable operation.

Inventive Principle:
Principle #19Periodic action

3Productivity

If logic level transitions occur at the same time, then the system operation is synchronized and simple, but power supply ripple is generated affecting system operation

Engineering Contradiction:
Improveoperation efficiencyVSAvoidpower supply ripple
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent segments the simultaneous logic level transitions into distributed transitions by assigning different phase clock signals to different transmitting circuits. The first transmitting circuit operates according to the first phase clock signal while the second transmitting circuit operates according to the second phase clock signal, spreading out the transitions to reduce power supply ripple.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240419208A1Signal transmitting system and signal transmitting method
Publication Date: 2024.12.19 REALTEK SEMICON CORP
  • US20240419208A1 patent drawing
  • US20240419208A1 patent drawing
  • US20240419208A1 patent drawing

AI summary

A signal transmitting system comprising: a first transmitting circuit, operating according to a first operation clock signal with a first phase; a second transmitting circuit, operating according to a second operation clock signal with a second phase, wherein the first phase and the second phase are different; and a multi-phase clock signal generating circuit, coupled to the first transmitting circuit and the second transmitting circuit, to generate the first operation clock signal and the second operation clock signal.