Multiphase Counter Circuit for Accurate High-Speed Image Sensing
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Solution Overview
Problem
Existing image sensors face challenges in achieving high-quality operation due to waveform collapse of count signals during high-speed counting operations, leading to degradation in counting accuracy.
Innovation Solution
The semiconductor device incorporates a comparator circuit, a counter circuit with a multiphase signal generator and flip-flop circuits, and a latch circuit to perform high-speed counting operations while maintaining signal waveform integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the counting operation by the counter circuit is sped up to achieve high-speed processing, then the processing speed is improved, but the waveform of the count values collapses and the accuracy of the counting operation degrades
Solution Approach 1:
The counter circuit is divided into multiple independent counter units (first counter unit, second counter unit, third counter unit, fourth counter unit) that operate in parallel. Each counter unit handles a portion of the counting operation, allowing the overall system to achieve high-speed processing while maintaining accuracy through distributed computation rather than a single overloaded counter.
Solution Approach 2:
The patent transitions from a single-dimensional sequential counting approach to a multi-dimensional parallel counting architecture. By introducing multiple counter units operating simultaneously with different clock signals (first clock signal, second clock signal, third clock signal, fourth clock signal), the system expands the operational dimension, enabling high-speed counting without waveform collapse.
2Reliability
If the counting operation is repeated multiple times at high speed to suppress noise by averaging, then the noise suppression is improved, but the waveform collapse and accuracy degradation occur more severely
Solution Approach 1:
The counter circuit is divided into multiple independent counter units (first counter unit, second counter unit, third counter unit, fourth counter unit) that operate in parallel. Each counter unit handles a portion of the counting operation, allowing the overall system to achieve high-speed processing while maintaining accuracy through distributed computation rather than a single overloaded counter.
Solution Approach 2:
The patent transitions from a single-dimensional sequential counting approach to a multi-dimensional parallel counting architecture. By introducing multiple counter units operating simultaneously with different clock signals (first clock signal, second clock signal, third clock signal, fourth clock signal), the system expands the operational dimension, enabling high-speed counting without waveform collapse.
Data Source
AI summary
A semiconductor device according to this disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit includes: a multiphase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop and second-stage and subsequent flip-flops, the first-stage flip-flop takes in an inverted signal of an output signal of a flip-flop in a final stage and each of the second-stage and subsequent flip-flops takes in an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of the count value.