Multiphase DCDC Converter with Distributed Error Amplifiers
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Solution Overview
Problem
In multiphase parallel DCDC circuits, the increasing number of phases leads to larger die areas, longer trace lengths, and increased parasitic capacitance and resistance, which deteriorate loop bandwidth and transient response, causing overshoot or undershoot during transient events.
Innovation Solution
The introduction of a multiphase parallel DCDC circuit structure with a loop operational amplifier EA unit and M drive units, where the drive unit connects the EA output to the COMP, reducing the length of output traces and parasitic capacitance and resistance, allowing the COMP to be placed closer to the power stage circuit, thereby enhancing loop bandwidth and transient response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of parallel phases is increased to improve output loading capability, then the output loading capability is improved, but the die area and trace length are increased, causing increased parasitic capacitance and resistance
Solution Approach 1:
The patent divides the control function into multiple independent error amplifiers (one per phase) rather than using a single shared EA. Each EA is locally positioned near its corresponding power stage, segmenting the control path and enabling independent optimization of each phase's trace length and parasitic characteristics while maintaining high output loading capability through parallel operation
Solution Approach 2:
The patent transitions from a centralized EA architecture (single point control) to a distributed EA architecture (multiple points control). This dimensional change in control architecture allows each phase to have its own local EA, effectively reducing the trace length and parasitic elements in each control path while supporting high-phase parallel operation
2Reliability
If the trace length is increased to connect EA to power stage circuit, then the connection is established, but the parasitic capacitance and resistance are increased, causing lower loop bandwidth
Solution Approach 1:
The control path is segmented into local segments, with each error amplifier positioned near its corresponding power stage. This segmentation creates short, localized control traces for each phase, minimizing the cumulative trace length and associated parasitic capacitance and resistance, thereby maintaining high loop bandwidth
Solution Approach 2:
The error amplifier serves as a local intermediary between the feedback network and the power stage for each phase. By placing the EA locally rather than using long traces to a centralized EA, the intermediary function is achieved with minimal trace length, reducing parasitic effects and preserving loop bandwidth
3Loss of time
If the EA is disposed at center position of die to reduce delay, then the delay to power stage is reduced, but the trace length and parasitics are increased when connecting to multiple COMPs
Solution Approach 1:
The patent segments the control architecture so that each phase has its own dedicated error amplifier positioned locally near its power stage and COMP. This eliminates the need for long traces from a centralized EA to multiple COMPs, as each EA- COMP connection is short and localized, simultaneously achieving low delay and low parasitics
Solution Approach 2:
The patent changes from a centralized control dimension (single EA at die center) to a distributed control dimension (multiple EAs at phase locations). This dimensional transformation allows each control path to be optimized independently, achieving minimal trace length and parasitic elements for each phase while maintaining fast response
4Power
If the quantity of parallel phases is increased to reach tens or hundreds of amperes, then the output loading capability is improved, but the loop transient response deteriorates due to increased parasitics
Solution Approach 1:
By segmenting the control function into independent per-phase error amplifiers positioned locally, each phase's control path maintains low parasitic capacitance and resistance regardless of the total number of phases. This enables high output loading capability through parallel operation while preserving fast transient response speed in each individual phase
Solution Approach 2:
The patent implements a distributed EA architecture that provides more control resources (one EA per phase) than the minimal requirement (one shared EA). This excessive provision of control resources ensures that each phase can be independently optimized for fast transient response, even when the total number of phases is large
Data Source
AI summary
A multiphase parallel digital current (DC) to DC converter (DCDC) circuit includes a loop operational amplifier (EA) unit, N output-stage circuit units, and M drive units, where a drive unit corresponds to at least one output-stage circuit unit including a comparator (COMP) and a power stage circuit, an output end of the loop operational amplifier EA unit is connected to an input end of the drive unit, an output end of the drive unit is connected to an input end of a COMP in a corresponding output-stage circuit unit, and an output end of the COMP is connected to an input end of a power stage circuit in the same output-stage circuit unit, and an input end of the loop operational amplifier EA unit is connected to output ends of all the power stage circuits.