Asynchronous Clock Sampling for Uniform Multi-Phase Signal Delays
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Solution Overview
Problem
Conventional multi-phase signal generators struggle to accurately control the phase difference between adjacent signals due to process variations, leading to uneven phase differences that do not correspond to the desired one-fifth of the input signal period.
Innovation Solution
A semiconductor device with a delay circuit, clock generator, detector, and controller that adjusts the delay amount of multi-phase signals using an asynchronous clock signal to compare and correct phase differences, employing a counter, flip-flop, multiplier, subtractor, digital filter, and digitally controlled oscillator to generate and filter the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-phase signal generator compares input signal Vp0 and output signal Vp5 to control phase, then the control process is simple, but the phase difference between adjacent signals becomes uneven due to process variation
Solution Approach 1:
The patent introduces an asynchronous clock signal as an intermediary to mediate the phase comparison process. Instead of directly comparing the input signal with the output signal, the system uses the asynchronous clock to sample both signals and generate pulse signals that represent their phase relationships. This intermediary approach enables more accurate phase difference measurement and control while avoiding the limitations of direct signal comparison.
Solution Approach 2:
The patent replaces the conventional direct signal comparison mechanism with a sampling-based measurement system. By using the asynchronous clock to sample the input and output signals, the system transforms the continuous phase comparison problem into discrete pulse signal generation and analysis, enabling more precise control of phase differences between adjacent multi-phase signals.
2Measurement precision
If high-frequency clock signal is used for sampling to achieve accurate phase measurement, then measurement precision improves, but power consumption increases
Solution Approach 1:
The patent changes the fundamental parameter of the clock signal from synchronous to asynchronous, and optimizes its frequency to be lower than the input signal frequency. This parameter change allows the system to achieve accurate phase measurements through multiple samples over time, rather than requiring a single high-frequency sampling point, thereby reducing power consumption while maintaining or improving measurement precision.
Solution Approach 2:
The patent employs periodic sampling using the asynchronous clock signal to measure phase differences over multiple cycles. Instead of using a single high-frequency sampling instant, the system accumulates phase information through repeated lower-frequency sampling, which reduces the instantaneous power requirements while achieving high measurement accuracy through statistical accumulation.
Data Source
AI summary
A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.