Multi-Phase Fractional Divider for Low-Jitter PLL Feedback
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Solution Overview
Problem
Existing frequency division methods in high-performance computing and communication systems, such as those using integer dividers with large division ratios, limit the design space and result in coarse frequency resolution and significant phase errors and jitter, especially in PLLs with high bandwidth and open-loop gain.
Innovation Solution
A Multi-Phase Multi-Modulus Frequency Divider (MMFD) is introduced, combining a multiplexer, bi-directional phase-rotator, multi-modulus divider, and sigma-delta modulator to dynamically modulate the PLL feedback divider ratio, enabling fractional division with reduced phase error and jitter, and offering glitch-free and low-power operation across a wide divider range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an integer divider with large division ratio is used to generate fine frequency resolution, then the system clock resolution is improved, but the phase error and jitter increase significantly
Solution Approach 1:
The patent segments the frequency division function into multiple parallel integer dividers with different division ratios (e.g., N, N+1, N+2). By selecting and combining outputs from these segmented dividers, the system achieves fine frequency resolution without using a single large division ratio that would cause excessive phase error and jitter. This segmentation allows the PLL to maintain stability while achieving precise frequency control.
Solution Approach 2:
The patent implements dynamic switching between different integer dividers based on the desired output frequency. The frequency synthesizer dynamically selects which divider ratio to use and adjusts the PLL control accordingly. This dynamic adaptation allows the system to maintain optimal phase error and jitter performance across a wide frequency range, rather than being constrained by a fixed large division ratio.
2Measurement precision
If a lower reference clock frequency is used with large integer division ratio, then finer system clock frequency is generated, but the design space is limited and resolution is constrained
Solution Approach 1:
The patent creates a universal frequency synthesis solution that works across multiple reference clock frequencies and output frequency ranges. By using multiple integer dividers with different ratios and implementing dynamic selection, the system can achieve fine frequency resolution whether using a low reference frequency with large division or a higher reference frequency with smaller division. This multi-functional approach eliminates the constraint of needing to choose between reference frequency and division ratio, providing versatility across the entire design space.
Solution Approach 2:
The patent changes the parameter of division ratio from a single fixed large value to multiple selectable values (N, N+1, N+2, etc.). This parameter change allows the system to adapt to different reference clock frequencies and output frequency requirements. Instead of being locked into a specific reference frequency to achieve fine resolution, the system can adjust the division ratio parameter dynamically, expanding the design space and providing flexibility in system configuration.
3Measurement precision
If multiple integer dividers with different ratios are used to achieve fine frequency resolution, then frequency precision is improved, but the circuit complexity increases
Solution Approach 1:
The patent merges multiple integer dividers into a unified frequency synthesis architecture where the dividers share common inputs and control logic. The outputs of multiple dividers are combined through a selection mechanism controlled by the PLL. This merging approach allows the system to achieve fine frequency precision using multiple dividers while reducing overall circuit complexity compared to having completely separate divider circuits for each function. The shared architecture minimizes redundant components and simplifies the overall design.
Data Source
AI summary
Described is an apparatus comprising: a multi-modulus divider; and a phase provider to receive a multiphase periodic signal and operable to rotate phases of the multiphase periodic signal to generate an output which is received by the multi-modulus divider.