Multiphase Divider Reset Sequencing for Stable Phase Relations
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Solution Overview
Problem
Conventional multiphase divider circuits fail to maintain proper phase relations after multiple frequency divisions, leading to divided output signals that are no longer valuable due to non-monotonic phase increases, and lack a well-defined initial state, resulting in uncertain phase relations at outputs.
Innovation Solution
A multiphase divider circuit comprising multiple differential frequency dividers with phase inversions and a reset signal generator, which ensures proper phase preservation and maximizes timing margins by synchronizing reset signals, maintaining phase relations and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple frequency divisions are performed using conventional multiphase divider circuits, then the frequency is reduced to desired levels, but the phase relations become non-monotonic and output phases fall outside the initial set
Solution Approach 1:
The patent applies preliminary action by performing phase inversion at specific stages before final output generation. The phase inversion operation is executed in advance within the division process to prevent phase relations from becoming non-monotonic, ensuring that output phases remain within the initial set even after multiple frequency divisions.
Solution Approach 2:
The patent directly applies inversion by introducing phase inversion operations that flip the phase relationships in reverse to counteract the non-monotonic phase drift that naturally occurs during multiple frequency divisions. This inversion mechanism ensures that the phase relations remain monotonic and output phases stay within the original phase set.
2Device complexity
If conventional multiphase divider circuits are used without reset synchronization, then the circuit structure is simple, but the initial state is undefined leading to uncertain phase relations at outputs
Solution Approach 1:
The patent applies preliminary action by implementing synchronized reset operations that are timed to occur at specific phase alignment points. The reset signal is generated and applied in advance to establish a well-defined initial state before the frequency division process begins, ensuring deterministic phase relations at the outputs.
Solution Approach 2:
The patent applies feedback by using the phase information from the division process to control the timing of reset signals. The reset synchronization mechanism monitors phase relations and applies resets at optimal moments to maintain deterministic initial states, creating a feedback loop that ensures reliability.
3Stability of the object's composition
If phase inversions are added to preserve monotonic phase increases, then phase relations are maintained, but the device complexity increases
Solution Approach 1:
The patent applies partial action by implementing phase inversion only at specific stages where it is most needed to correct non-monotonic phase relations, rather than applying it uniformly throughout the entire division chain. This selective approach maintains phase monotonicity while minimizing the added complexity.
Data Source
AI summary
An example embodiment disclosed herein enables at least one frequency divider chain of a multiphase divider circuit to ensure proper phase relations after multiple frequency divisions. Another example embodiment enables a unique reset sequence to maximize a timing margin for reset signals of the at least one frequency divider chain and, thus, maximizes a bandwidth of the multiphase divider circuit.