Multiphase DLL Clock Selection to Cut Lock Time and Current
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Solution Overview
Problem
Existing DLL circuits in synchronous dynamic random access memory devices consume high current and have long locking times due to their requirement for significant phase locking operations, leading to increased circuit area and potential harmonic locking issues.
Innovation Solution
A DLL circuit design that includes a multiphase clock signal generating unit and a multiphase clock signal selecting unit, utilizing a voltage controlled oscillator and a DLL control unit to produce and synchronize multiphase clock signals with a reference clock signal, reducing current consumption and locking time by enabling phase synchronization through a bias voltage adjustment and feedback mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DLL circuit uses a voltage controlled delay line to lock onto a signal with clock period N times larger than incoming signal, then multiphase clock signal generation is achieved, but harmonic locking problems occur due to restriction of locking range
Solution Approach 1:
The patent divides the locking process into two independent stages: a reference loop that generates multiphase clock signals with correct frequency relationships, and a main loop that locks the output clock to the input clock. This segmentation allows each loop to operate within its optimal locking range, preventing harmonic locking issues while maintaining multiphase signal generation capability.
Solution Approach 2:
The patent introduces a reference loop as an intermediary mechanism between the input clock and the main DLL loop. This reference loop generates intermediate multiphase clock signals that serve as a bridge, enabling the main loop to lock accurately without directly dealing with the large frequency multiplication factor that causes harmonic locking problems.
2Reliability
If a DLL circuit implements comprehensive phase locking operations to synchronize multiphase clock signals, then clock signal synchronization is improved, but current consumption increases significantly
Solution Approach 1:
The patent segments the phase locking function into two separate loops with different purposes and complexity levels. The reference loop handles frequency relationship establishment with moderate current consumption, while the main loop handles phase synchronization with lower current consumption. This segmentation reduces the total current consumption compared to a single comprehensive phase locking circuit.
Solution Approach 2:
The patent applies partial phase locking action by having the reference loop lock only frequency relationships and the main loop lock only phase relationships. Neither loop performs complete comprehensive phase locking, which reduces the overall current consumption while still achieving the desired synchronization through the coordinated action of both loops.
3Reliability
If a DLL circuit performs extensive phase locking operations to achieve signal synchronization, then locking accuracy is improved, but locking time increases
Solution Approach 1:
The patent divides the locking process into two concurrent loops that operate in parallel. The reference loop quickly establishes frequency relationships, while the main loop simultaneously performs phase locking. This segmentation allows both frequency and phase synchronization to occur concurrently rather than sequentially, reducing total locking time while maintaining high synchronization accuracy.
Solution Approach 2:
The reference loop performs preliminary frequency relationship establishment before the main phase locking operation completes. This preliminary action prepares the system in advance, so when the main loop begins phase locking, the frequency relationships are already correct, allowing faster convergence to the final synchronized state.
Data Source
AI summary
A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled.