Multi-Phase Delay Locked Loop for Wider Timing Margin
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits in semiconductor memory devices face reduced operation margin under high frequency operations or changes in conditions such as pressure, temperature, or input voltage, leading to decreased reliability.
Innovation Solution
A semiconductor memory device with a multi-phase delay locked loop that generates multiple clock signals and uses a phase control block to compare and adjust these signals, enabling shifting operations to enhance clock delay compensation and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-phase DLL circuit is used, then the circuit structure is simple, but the operation margin is reduced under high frequency operations or varying conditions
Solution Approach 1:
The delay line is divided into multiple segments (first delay line and second delay line) that can be independently controlled. Each segment has its own delay control signal, allowing separate adjustment of delay amounts. This segmentation enables the DLL to achieve finer phase control and maintain operation margin under varying conditions while managing circuit complexity through modular design.
Solution Approach 2:
The DLL circuit implements dynamic delay control by using phase detection to continuously monitor the phase difference between output and reference clocks, and dynamically adjusting the delay amounts of individual delay line segments. This dynamic adjustment mechanism allows the circuit to adapt to high frequency operations and varying conditions, maintaining optimal operation margin without requiring an overly complex fixed structure.
2Reliability
If delay control is applied to compensate for internal clock delay, then clock skew is compensated and data output timing is synchronized, but the operation margin decreases under high frequency or varying conditions
Solution Approach 1:
The delay compensation function is divided into multiple independent delay segments, each controllable by separate delay control signals. This allows selective adjustment of different delay portions to compensate for specific timing issues while maintaining adaptability to various operating conditions through independent control of each segment.
Solution Approach 2:
The invention changes the delay parameter of each delay line segment independently based on detected phase differences and operating conditions. By adjusting delay amounts dynamically according to frequency and environmental variations, the circuit maintains both timing synchronization and adaptability across different operating scenarios.
3Reliability
If a multi-phase delay locked loop is implemented, then operation margin is increased and reliability is improved, but the device complexity increases
Solution Approach 1:
The multi-phase DLL is implemented by segmenting the delay line into multiple independently controllable sections. Each segment can be adjusted to create different phase outputs, achieving multi-phase functionality without requiring completely separate DLL circuits. This segmentation approach increases operation margin through multiple phase options while controlling complexity through shared circuit resources.
Solution Approach 2:
The delay line segments serve multiple functions: they can be individually adjusted to create multiple phase outputs for different operational modes, compensate for timing skew, and adapt to varying conditions. This multi-functionality allows a single segmented delay structure to replace what would otherwise require multiple separate circuits, improving reliability without proportionally increasing complexity.
Data Source
AI summary
A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.