Multiphase Time Measurement Circuit for Sub-Clock Event Timing
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Solution Overview
Problem
Existing time measurement circuits face limitations in accuracy and resolution when measuring the time elapsed between events, particularly in high-frequency applications like wireless power transmission and switching mode power converters, due to the constraints of clock period and switching losses.
Innovation Solution
A time measurement circuit utilizing a multiphase clock generator and phase sampling circuit to generate a phase value indicative of the time elapsed between a clock signal edge and an asynchronous event, employing multiple phase-shifted clock phases to achieve high-resolution timing with improved precision and control over PWM signal duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single-phase clock signal is used for time measurement, then the device complexity is low, but the measurement precision is limited by the clock period
Solution Approach 1:
The clock signal is segmented into multiple phase-shifted versions (e.g., 4 phases shifted by 90 degrees each). Each phase captures timing information for a specific time window, allowing the measurement of sub-clock-period intervals by determining which phase captured the event and what fraction of the clock period has elapsed within that phase's window.
Solution Approach 2:
The time measurement is extended from a single dimension (clock period) to multiple dimensions by introducing phase shifts. The measurement now includes both the phase index (which phase captured the event) and the fractional clock period within that phase, effectively creating a multi-dimensional time measurement space that achieves higher resolution without increasing clock frequency.
2Measurement precision
If the clock frequency is increased to improve measurement resolution, then the measurement precision improves, but the power consumption increases
Solution Approach 1:
Instead of changing the clock frequency parameter, the invention changes the phase distribution parameter by generating multiple phase-shifted versions of the same frequency clock signal. This allows the system to achieve higher effective measurement resolution without increasing the clock frequency, thereby avoiding the proportional increase in power consumption that would result from higher frequency operation.
3Measurement precision
If the clock frequency is increased to improve measurement resolution, then the measurement precision improves, but switching losses increase
Solution Approach 1:
The clock signal is segmented into multiple phase-shifted versions (e.g., 4 phases shifted by 90 degrees each). Each phase captures timing information for a specific time window, allowing the measurement of sub-clock-period intervals by determining which phase captured the event and what fraction of the clock period has elapsed within that phase's window.
Solution Approach 2:
The time measurement is extended from a single dimension (clock period) to multiple dimensions by introducing phase shifts. The measurement now includes both the phase index (which phase captured the event) and the fractional clock period within that phase, effectively creating a multi-dimensional time measurement space that achieves higher resolution without increasing clock frequency.
4Measurement precision
If a simple counter circuit is used, then the device complexity is low, but the measurement precision is limited
Solution Approach 1:
The clock signal is segmented into multiple phase-shifted versions (e.g., 4 phases shifted by 90 degrees each). Each phase captures timing information for a specific time window, allowing the measurement of sub-clock-period intervals by determining which phase captured the event and what fraction of the clock period has elapsed within that phase's window.
Solution Approach 2:
The time measurement is extended from a single dimension (clock period) to multiple dimensions by introducing phase shifts. The measurement now includes both the phase index (which phase captured the event) and the fractional clock period within that phase, effectively creating a multi-dimensional time measurement space that achieves higher resolution without increasing clock frequency.
Data Source
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AI summary
A time measurement circuit is described. The time measurement circuit comprises a multiphase clock generator and a phase sampling circuit (30b). The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases (φ0...φn-1), wherein one of the phase shifted clock phases (φ0...φn-1) represents a reference clock signal (TMR_CLK). The phase sampling circuit (30b) is configured to generate a phase value (CMP_PH_FIN) indicative of a number of fractions 1/n of the clock period of the clock phases (φ0...φn-1)elapsed between an edge of the reference clock signal (TMR_CLK) and an instant when an asynchronous event signal (AE) is set. Specifically, the phase sampling circuit (30b) comprises various sub-circuit. A first sub-circuit (FFa) determined for each (φi) of the phase shifted clock phases (φ0...φn-1) a respective first control signal indicating whether the respective clock phase (φi) was set to high or low at the instant when said asynchronous event signal (AE) was set. A second sub-circuit (FFb) determines for each (φi) of the phase shifted clock phases (φ0... φn-1),a respective second control signal (CMP_PH(i)) corresponding to a synchronized version of the respective first control signal. A third sub-circuit (AND) associates with each (φi) of the phase shifted clock phases (φ0...φn-1) a further clock phase (φi-1) and determine for each (φi) of said phase shifted clock phases (φ0...φn-1) a respective third control signal as a function of the second control signals (CMP_PH(i)) associated with the respective phase shifted clock phase (φi) and the respective further clock phase (φi-1). A fourth sub-circuit (FFc) determines for each (φi) of the phase shifted clock phases (φ0...φn-1) a respective fourth control signal (CMP_PH_FIN(i)) corresponding to a synchronized version of the respective third control signal.