Multi-Phase Flash ADC Sampling Without Analog Demultiplexing
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Solution Overview
Problem
High-speed full flash ADCs face challenges with short track and latch times, leading to power dissipation and performance issues, while time-interleaved ADCs require an analog demultiplexer, complicating clock distribution and increasing power consumption.
Innovation Solution
The proposed ADC employs a parallel multi-phase sample unit with a delay-locked loop to generate incrementally delayed clock signals, allowing for lower system clock rates and eliminating the need for an analog demultiplexer, enabling efficient clock distribution and higher effective sample rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to satisfy Nyquist criteria, then the sampling rate is improved, but the track and latch times become too short causing comparator performance degradation and extreme power dissipation
Solution Approach 1:
The patent divides the sampling process into multiple phases by using a parallel multi-phase sample unit that generates multiple incrementally delayed clock signals (Φ0, Φ1, Φ2, Φ3) within a single clock period. Each phase processes a portion of the reference levels, allowing the system to achieve high effective sampling rates while each individual comparator operates with adequate track and latch times.
Solution Approach 2:
The patent transitions from a single-clock-domain operation to a multi-phase time domain by introducing incremental time delays within the clock period. The delay-locked loop generates phased clock signals that stagger the operation of different comparator groups, effectively adding a time-phase dimension to the sampling process.
2Productivity
If the clock frequency is increased to satisfy Nyquist criteria, then the sampling rate is improved, but the comparator cannot properly amplify the input signal due to insufficient track time
Solution Approach 1:
The patent segments the comparator bank into multiple groups, each operated by a different phase of the multi-phase clock signals. This allows each comparator group to have sufficient track time within its assigned phase while the overall system achieves high sampling rates through the combination of all phases.
Solution Approach 2:
The patent employs periodic multi-phase clock signals with incremental delays to sequentially activate different comparator groups. Each phase provides a complete track-latch cycle at a relaxed timing, and the periodic repetition of these phases achieves the high effective sampling rate required by the Nyquist criteria.
3Productivity
If the clock frequency is increased to satisfy Nyquist criteria, then the sampling rate is improved, but the comparator remains in metastable state due to insufficient latch time
Solution Approach 1:
The patent uses periodic multi-phase clock signals where each phase provides an adequate latch time for its assigned comparators. The metastable state is avoided because each comparator group operates in a complete, non-overlapping track-latch cycle within its phase window, and the periodic repetition ensures stable settling before the next phase begins.
4Productivity
If time-interleaved ADC configuration is used to increase effective sample rate, then the sampling rate is improved, but an analog demultiplexer is required complicating clock distribution and increasing power consumption
Solution Approach 1:
The patent merges the functions of multiple ADC operations into a single integrated structure. By using a parallel multi-phase sample unit that directly generates phased clock signals for multiple comparator groups, the patent eliminates the need for a separate analog demultiplexer that would be required in traditional time-interleaved configurations.
Solution Approach 2:
The patent extracts and eliminates the analog demultiplexer component from the system architecture. Instead of using a demultiplexer to distribute the input signal to multiple ADCs, the patent directly distributes phased clock signals to comparator groups within a single ADC structure, removing the problematic component entirely.
Data Source
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AI summary
An analogue-to-digital converter (ADC), comprising - an input unit configured to receive an analogue input signal; - a reference unit, which is connected with the input unit and configured to provide a set of 2n-1 analogue reference signals, the set of reference signals as a whole forming a representation of a current amplitude of the input signal; and - a parallel multi-phase sampling unit, hereinafter PMSU, which is connected with the reference unit and which is configured to receive or generate a clock signal and to periodically generate and provide at its output a set of 2n-1 m-bit wide digital output signals based on the set of reference signals, each digital output signal being indicative of the values of a respective reference signal at the time of the clock signal and at the times of m incremental time delays within a clock period of the clock signal.