Multi-Phase Frequency Multiplier for Harmonic-Suppressed LO Generation
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Solution Overview
Problem
Conventional schemes for generating local oscillator signals at millimeter wave frequencies, such as 60 GHz, face challenges in achieving good tuning range, phase noise, and precise quadrature signals due to high frequency operation and low power availability from CMOS devices, making it advantageous to operate at a lower frequency and use a frequency multiplier to drive mixers in the receive and transmit chain.
Innovation Solution
A method involving the generation of multiple signals with specific phases and amplitudes to drive a set of transistors, resulting in an output signal frequency multiplied by the input signal frequency, utilizing a frequency multiplier comprising transistors with a common voltage source and drain, effectively eliminating fundamental and even-order harmonics to produce a signal at the desired frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional schemes are used to generate local oscillator signals at millimeter wave frequencies, then the LO signal can be generated directly, but the tuning range, phase noise, and signal precision deteriorate due to high frequency operation and low power availability
Solution Approach 1:
The frequency multiplication process is segmented into multiple stages, with each transistor contributing to a specific harmonic component. The n-transistor circuit divides the frequency multiplication task, where each transistor processes a phase-shifted version of the input signal, enabling efficient generation of the nth harmonic while maintaining signal quality
Solution Approach 2:
The patent introduces an intermediary frequency multiplication stage between the low-frequency LO source and the millimeter wave mixer. The multi-phase oscillator circuit acts as a mediator that converts the low-frequency input signal into the required high-frequency signal, avoiding direct operation at millimeter wave frequencies while achieving the desired output
2Productivity
If a frequency multiplier is used to generate millimeter wave signals from a lower frequency source, then the tuning range and power efficiency improve, but unwanted harmonic components are generated that must be eliminated
Solution Approach 1:
The patent extracts only the desired nth harmonic component from the frequency multiplication process while eliminating unwanted harmonic components. The multi-phase oscillator configuration and transistor arrangement are specifically designed to cancel out fundamental and even-order harmonics, extracting only the useful frequency component for the millimeter wave application
Solution Approach 2:
The patent employs asymmetric phase distribution among the n transistors, with each transistor receiving input signals with specific phase relationships. This asymmetric configuration ensures that only the nth harmonic adds constructively at the output, while other harmonics cancel out, achieving harmonic suppression through deliberate phase asymmetry
3Power
If active multipliers are used instead of passive multipliers, then conversion gain and bandwidth improve, but power consumption increases and efficiency decreases due to power loss at unwanted harmonics
Solution Approach 1:
The patent converts what would normally be wasted energy at unwanted harmonic frequencies into a beneficial cancellation effect. By carefully designing the phase relationships among the n transistors, the energy that would be lost at fundamental and even-order harmonics is instead used to create destructive interference at those frequencies, while constructively adding at the desired nth harmonic frequency
Data Source
AI summary
A method of generating an output signal from an input signal includes a step of generating a set of n signals, n being an integer greater than or equal to 3, by generating a signal for each integer i such that 0≦i≦(n−1), each signal within the set having the same frequency and approximately equal amplitude and a phase equal to (360/n)i degrees. The method also includes a step of inputting each of the set of n signals to a gate terminal of a corresponding one of a set of n transistors. Each of the transistors has a source terminal electrically connected to a common voltage drain and each of the transistors has a drain terminal electrically connected to a coupling. The coupling is electrically connected to a common voltage source. The output signal at the coupling has a frequency equal to the frequency of the input signal multiplied by n.