Multi-Phase Gate Driving Circuit for Stable Low-Power Displays
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Solution Overview
Problem
Integrated gate driving circuits using amorphous silicon TFTs face challenges due to low carrier mobility, leading to high power consumption and instability, particularly under electric stress, which limits their application in high-performance displays.
Innovation Solution
A gate driving circuit design utilizing multi-phase clock signals to reduce circuit complexity and power consumption, achieved by using a few transistors and optimizing clock signal phases to improve stability and reduce noise voltage, thereby enhancing the reliability and efficiency of the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional two-phase clock gate driving circuits are used to enhance driving ability, then the driving capability is improved, but the circuit complexity and power consumption increase significantly
Solution Approach 1:
The patent changes the clock signal parameter from two-phase to multi-phase (four or more phases), which fundamentally alters the timing control mechanism. This allows the gate driving circuit to achieve enhanced driving capability while reducing circuit complexity by utilizing phase-shifted clock signals to control transistor switching sequences more efficiently
Solution Approach 2:
The patent introduces dynamic phase shifting of clock signals to control the switching timing of transistors. By dynamically adjusting which transistor is activated at which phase, the circuit achieves flexible control of driving capability without requiring additional static circuit components, thus improving performance while maintaining simplicity
2Power
If two-phase clock gate driving circuits are used to enhance driving ability, then the driving capability is improved, but the power consumption increases
Solution Approach 1:
The patent employs periodic multi-phase clock signals to control transistor switching. By using four or more phases instead of two, the circuit achieves more efficient periodic operation where transistors are switched on and off more precisely, reducing unnecessary current flow and lowering overall power consumption while maintaining enhanced driving capability during active periods
Solution Approach 2:
Changing from two-phase to multi-phase clock signaling fundamentally alters the power consumption characteristics. The increased number of phases allows for more precise timing control, reducing the duration that transistors remain in high-power states and enabling the circuit to achieve better power-efficiency ratio
3Power
If two-phase clock gate driving circuits are used to enhance driving ability, then the driving capability is improved, but the stability deteriorates due to threshold voltage shift
Solution Approach 1:
The patent uses dynamic multi-phase clock signaling to create more varied switching patterns that prevent prolonged static stress on individual transistors. By distributing the driving tasks across multiple phases and different transistor combinations, the circuit reduces cumulative threshold voltage shifts and improves long-term stability while maintaining high driving capability during each phase
Solution Approach 2:
The patent employs preliminary phase shifts and pre-charging/discharging sequences built into the multi-phase clock architecture. These preliminary actions prepare the transistor states in advance, ensuring that threshold voltage shifts are compensated for before they can cause instability, thereby improving reliability while maintaining enhanced driving capability
Data Source
AI summary
A gate driving circuit unit, a gate driving circuit and a display device are disclosed. The gate driving circuit unit comprises: a first clock signal control module, an input signal control module, a third clock signal control module and a fourth clock signal control module, wherein the first clock signal control module comprises a driving unit and a clock feed-through suppressing unit. The driving unit transmits a first clock signal to an output port after being switched on. The clock feed-through suppressing unit couples the control end of the driving unit to a signal output interface under control of the first clock signal. The input signal control module provides the driving voltage for the driving unit under control of an input pulse signal. The third clock signal control module provides the shutdown voltage for the driving unit.