Multi-Phase LDPC Decoding for Low Complexity and Lower Error Floors
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Solution Overview
Problem
Current decoding technologies for Low Density Parity Check (LDPC) codes face challenges in high decoding complexity, error floors, and increased cost due to complex algorithms and hardware requirements, particularly in high-speed communication systems.
Innovation Solution
The development of low-power, low-cost digital Min-Sum decoders and stochastic decoders with delayed stochastic decoding techniques, along with multi-phase decoding methods that reduce hardware complexity and error floors without requiring knowledge of trapping set structures, allowing for improved error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional belief propagation decoding is used for LDPC codes, then error correction performance approaches channel capacity, but decoding complexity becomes too high for practical implementation
Solution Approach 1:
The patent applies parameter changes by transforming the decoding algorithm from traditional belief propagation to Min-Sum decoding, which changes the computational parameters and operations. This substitution replaces complex logarithmic calculations with simpler minimum operations, reducing hardware complexity while maintaining acceptable error correction performance for practical LDPC code implementations
2Device complexity
If decoding algorithms are optimized for lower complexity, then hardware cost and power consumption decrease, but error floors increase
Solution Approach 1:
The patent applies segmentation by dividing the decoding process into multiple phases: a first phase using Min-Sum decoding for low complexity operation, and a second phase that activates only when decoding failure is detected. This segmented approach allows the system to operate at low complexity normally while providing a safety net to address error floors when they occur, thus resolving the contradiction between hardware complexity and error floor performance
3Reliability
If iterative decoding is implemented to improve error correction, then performance approaches Shannon limit, but processing time and latency increase
Solution Approach 1:
The patent applies partial action by implementing a two-phase decoding strategy where the first phase performs a limited number of iterations using Min-Sum decoding. This partial execution is sufficient for most cases, and only when failure is detected does the system activate the second phase. This approach reduces average decoding latency while maintaining error correction capability, as the majority of decodings complete in the faster first phase
Data Source
AI summary
Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates. Accordingly encoders with reduced complexity, reduced power consumption and improved performance are disclosed with various improvements including simplifying communications linking multiple processing nodes by passing messages where pulse widths are modulated with the corresponding message magnitude, delaying a check operation in dependence upon variable node states, running the decoder multiple times with different random number generator seeds for a constant channel value set, and employing a second decoder with a randomizing component when the attempt with the first decoder fails.