Multiphase Level Shifter Timing for Low Through Current
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Solution Overview
Problem
Conventional level shifters experience increased power consumption due to through current and reduced phase precision caused by overlapping ON periods of NMOS and PMOS transistors, leading to deteriorated voltage conversion performance.
Innovation Solution
A multiphase level shift system is designed with n level shifters, each featuring a first NMOS and PMOS transistor, where the PMOS transistor's gate receives an output signal delayed by a phase amount X from another level shifter, and additional transistors and delay elements are used to eliminate overlapping current periods, thereby reducing power consumption and improving phase precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional level shifters are used with overlapping ON periods of NMOS and PMOS transistors, then voltage conversion is achieved, but power consumption increases due to through current
Solution Approach 1:
The gate of the PMOS transistor is driven by a clock signal that is preliminarily delayed by a specific phase amount (e.g., 45° in an 8-phase system) relative to the NMOS gate clock signal. This preliminary phase shifting ensures that the PMOS transistor turns on before the NMOS transistor turns off, eliminating the overlapping conduction period and preventing through current flow from power supply to ground.
Solution Approach 2:
The invention changes the phase parameter of the clock signal driving the PMOS gate relative to the NMOS gate clock signal. By adjusting this phase difference to a specific value (0° < phase amount < 180°), the conduction periods of the two transistors are desynchronized, eliminating simultaneous conduction while maintaining proper voltage conversion function.
2Measurement precision
If conventional level shifters are used with overlapping ON periods, then voltage conversion is achieved, but phase precision deteriorates
Solution Approach 1:
By preliminarily delaying the PMOS gate clock signal by a controlled phase amount, the invention ensures that the PMOS transistor begins conducting before the NMOS transistor stops conducting. This preliminary action eliminates the overlapping period, thereby maintaining sharp signal edges and high phase precision while preventing the through current that would increase power consumption.
Solution Approach 2:
The invention utilizes periodic clock signals with a specific phase relationship between the NMOS and PMOS gate drives. By establishing a regular phase difference pattern (where the PMOS clock leads the NMOS clock by a controlled amount), the system achieves consistent non-overlapping conduction cycles, maintaining both low power consumption and high phase precision across all operating cycles.
3Loss of energy
If the phase delay amount is increased to eliminate overlapping current periods, then power consumption is reduced, but signal rising and falling performance may deteriorate
Solution Approach 1:
The invention optimizes the phase delay parameter to a specific range (0° < phase amount < 180°, preferably around 45° for 8-phase systems). This optimized parameter value is sufficient to eliminate overlapping conduction and reduce power consumption, while being small enough to maintain fast signal rising and falling edges by minimizing the additional delay introduced to the voltage conversion process.
Data Source
AI summary
Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.