Multiphase LO Layout With Matched Routing for Harmonic Rejection

The patent employs asymmetric routing design where the interconnect structure is specifically configured to achieve matched routing lengths from multiple phase generators to mixer inputs, rather than using symmetric mesh routing. This asymmetric layout optimizes signal paths to minimize parasitic effects while maintaining functional requirements.

The patent transitions from planar mesh routing to a three-dimensional interconnect structure utilizing multiple metal layers. Phase generators are distributed across different layers and connected to mixer inputs through vertical and horizontal interconnects, allowing routing length matching that is not constrained by two-dimensional layout limitations.

The asymmetric interconnect design specifically optimizes signal paths to achieve matched routing lengths, which ensures equal parasitic resistance and capacitance values. This matching prevents differential signal degradation and maintains harmonic rejection performance while minimizing unnecessary power dissipation from unbalanced routing.

The patent optimizes interconnect parameters including conductor width, thickness, and material composition to minimize parasitic resistance and capacitance. By carefully controlling these physical parameters, the design achieves low power consumption while maintaining the required harmonic rejection capability.

The patent utilizes three-dimensional interconnect structures with multiple metal layers to connect distributed phase generators to mixer inputs. This vertical dimension provides additional routing paths that can accommodate phase generator distribution while maintaining matched routing lengths, overcoming the limitations of planar layouts.

The interconnect structure is segmented into multiple sections across different metal layers, allowing independent optimization of each segment. This segmentation enables flexible routing paths that can accommodate distributed phase generators while ensuring each signal path has matched length and minimized parasitics.

By utilizing multiple metal layers, the patent reduces the horizontal chip area required for routing length matching. Signal paths can extend vertically through different layers rather than requiring large horizontal distances, thereby compacting the overall layout while maintaining routing length match precision.

The interconnect structure employs nested routing where signal paths are embedded within multiple metal layers, with lower layers providing foundational routing and upper layers providing additional routing flexibility. This nesting allows efficient use of chip area by utilizing the vertical stack rather than expanding horizontally.