Multi-Phase Locked-Loop Circuit for Precise DCO Phase Synchronization
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Solution Overview
Problem
Locked-loop circuits, such as phase-locked loops, face errors due to small changes in sampling time that affect the phase and frequency matching between the reference clock and the output signal, leading to inaccuracies in timing signal generation.
Innovation Solution
A method is introduced that includes a loop filter and a digitally-controlled oscillator (DCO) with a time-to-digital converter (TDC) and phase synchronization circuitry, which determines a calibration codeword and scaling factor to adjust the loop filter parameters, reducing sampling errors by applying phase adjustments based on edge detection signals from multiple sampling clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single sampling clock is used to sample the reference clock, then the circuit complexity is low, but sampling errors occur due to small changes in sampling time affecting phase and frequency matching
Solution Approach 1:
The patent divides the sampling process into multiple segments by using N sampling clocks with different phases (Φ0 through ΦN-1) instead of a single sampling clock. Each sampling clock samples the reference clock at a different phase point, creating multiple samples per reference clock cycle. This segmentation allows the system to capture phase information more accurately across the entire clock cycle, resolving the sampling errors caused by timing variations while maintaining manageable circuit complexity through systematic phase distribution.
Solution Approach 2:
The patent transitions from single-dimensional sampling (one sampling clock) to multi-dimensional sampling by introducing phase as an additional dimension. The N sampling clocks are distributed across different phases within a clock cycle, creating a phase-domain expansion. This dimensional change allows the system to measure phase differences more precisely by comparing samples taken at different phase angles, effectively converting a timing accuracy problem into a phase comparison problem that can be solved through multi-phase sampling.
2Reliability
If multiple sampling clocks with different phases are used, then sampling errors are reduced, but the device complexity increases
Solution Approach 1:
The patent merges the functionality of N separate sampling operations into a unified multi-phase sampling system. Instead of treating each sampling clock as an independent complex component, the system combines them into a coordinated set of phases that work together to provide comprehensive phase information. The phase information from all N sampling clocks is integrated and processed collectively to determine the optimal DCO codeword, thereby improving reliability through combined information while managing complexity through unified processing.
Solution Approach 2:
The N sampling clocks serve multiple functions simultaneously: they sample the reference clock at different phases, provide phase information for accuracy improvement, and enable calibration of the DCO. This multi-functionality allows the system to achieve higher reliability without proportionally increasing complexity, as the same hardware infrastructure supports multiple operational requirements including sampling, phase measurement, and calibration operations.
3Adaptability or versatility
If the loop filter parameters are fixed, then the circuit is simple, but it cannot adapt to changing environmental conditions and DCO gain variations
Solution Approach 1:
The patent transforms the static loop filter configuration into a dynamic system where parameters can be adjusted based on operating conditions. The loop filter parameters are no longer fixed but are scaled according to the calibration factor determined from multi-phase sampling. This dynamic adjustment allows the loop filter to adapt to environmental changes and DCO gain variations, improving versatility while maintaining relatively simple circuitry through parameter scaling rather than complex reconfiguration.
Solution Approach 2:
The patent implements adaptability by changing the parameters of the loop filter based on calibration information obtained from multi-phase sampling. The calibration factor, derived from comparing phases across multiple sampling clocks, is used to scale the loop filter parameters appropriately. This parameter change approach enables the system to respond to environmental variations and DCO gain changes without requiring complex structural modifications, achieving adaptability through controlled parameter adjustment.
Data Source
AI summary
A locked-loop circuit includes phase synchronization circuitry to synchronize a DCO clock phase to a reference clock phase. Sampling circuitry sequentially samples the reference clock with each of N sampling clocks having offset phases, a first one of the N sampling clocks comprising a master sampling clock. Edge detection logic accumulates phase information from the multiple sampling clocks and determines, based on the accumulated phase information, whether any of the sampling clocks other than the master sampling clock correspond to edge detection signals that occurred early with respect to a rising edge of the master sampling clock. Index logic generates index values for any of the determined early edge detection signals. The index logic transfers the generated index values to a master phase transfer logic unit. Phase adjust logic adjusts the master clock phase based on a selected one of the generated index values.