Multiphase Memory Clock Correction for High-Speed Data Timing
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high-speed data output and storage due to clock signal delays, phase changes, and distortions, which affect the precision of data transfer and storage operations.
Innovation Solution
A memory interface that utilizes multi-level signaling and error correction blocks to synchronize data with multiple phases of the system clock, ensuring precise data transmission and storage by correcting duty cycle and quadrature phase errors, thereby enhancing the reliability and speed of read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-level signaling is used to increase data transfer speed, then productivity is improved, but measurement precision deteriorates due to clock signal delays and phase changes
Solution Approach 1:
The patent implements a feedback mechanism where the memory device measures timing indicators of received transitions and sends calibration data back to the memory controller. The controller uses this feedback to adjust duty cycle and phase of clock signals, creating a closed-loop system that maintains timing precision despite high-speed operation and signal degradation
Solution Approach 2:
The patent dynamically changes clock signal parameters (duty cycle and phase) based on measured timing indicators. The memory controller adjusts these parameters in real-time to compensate for delays and phase changes, allowing the system to maintain measurement precision while operating at high productivity levels
2Productivity
If the operating speed is increased to achieve high-speed data output, then productivity is improved, but reliability deteriorates due to clock signal distortions
Solution Approach 1:
The calibration process provides continuous feedback on timing accuracy, allowing the system to detect and correct distortions in clock signals. This feedback loop ensures that even at increased operating speeds, the system can maintain reliable data transfer by adjusting clock parameters based on actual performance measurements
Solution Approach 2:
The patent performs preliminary calibration of timing reference signals before normal data transfer operations. By pre-adjusting duty cycle and phase parameters based on initial measurements, the system establishes reliable timing foundations that enable high-speed operation without sacrificing data transfer reliability
3Measurement precision
If duty cycle and phase calibration is performed to improve timing precision, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent uses a single sampler to perform multiple functions: sampling data patterns, measuring timing indicators, and generating calibration data. This multi-functional approach achieves high timing precision without requiring separate dedicated circuits for each function, thereby limiting the increase in device complexity
4Device complexity
If a single sampler is used to measure timing indicators to simplify the device, then device complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
The single sampler achieves precise timing measurements by dynamically changing its sampling timing based on calibration data. By adjusting when the sampler takes measurements according to calibrated duty cycle and phase information, the system compensates for the limitation of having only one sampler, maintaining measurement precision while reducing device complexity
Data Source
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AI summary
A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.