Multiphase Oscillator PLL for Higher Phase Resolution

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Solution Overview

Problem

Conventional phase-locked loops often suffer from low resolution in phase difference detection, leading to unwanted effects like jitter due to low frequency components, particularly in digital phase-locked loops.

Innovation Solution

A circuit comprising a multiphase oscillator generating multiple output signals with the same frequency but different phase offsets, a feedback value generator, and a reference value generator, along with a loop filter to control the oscillator based on feedback and reference values, enhancing phase resolution by utilizing multiple phase outputs for alignment with a reference clock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional phase-locked loops are used with single-phase output, then device complexity is reduced, but phase resolution deteriorates causing jitter

Engineering Contradiction:
Improvephase resolutionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The oscillator is divided into multiple phase outputs (e.g., 4 phases) instead of a single phase. Each phase output provides a distinct timing reference point, allowing the phase detector to measure phase differences with higher resolution by selecting appropriate phase transitions, thereby reducing jitter without significantly increasing overall system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention adds a phase dimension to the output signals by generating multiple phase-shifted versions of the same frequency signal. This dimensional expansion from single-phase to multi-phase allows the system to achieve higher measurement precision in phase detection by utilizing multiple reference points across different phase angles.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If low resolution phase difference detection is used, then device complexity is reduced, but unwanted jitter and low frequency components are generated

Engineering Contradiction:
Improvedevice complexityVSAvoidjitter
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The phase detector continuously monitors the phase difference between the reference signal and the divided feedback signal from the voltage controlled oscillator. This feedback mechanism allows real-time adjustment of the oscillator frequency and phase, enabling the system to suppress jitter and eliminate low frequency components by correcting phase errors as they occur, thereby reducing harmful effects.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If multiple phase outputs are generated, then phase resolution is improved, but device complexity increases

Engineering Contradiction:
Improvephase resolutionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The multi-phase oscillator serves multiple functions simultaneously: it generates the primary clock signal, provides multiple phase references for high-resolution detection, and enables frequency division. This multi-functionality allows the system to achieve high phase resolution without proportionally increasing device complexity, as the same hardware structure supports multiple operational requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7847643B2Circuit with multiphase oscillator
Publication Date: 2010.12.07 INFINEON TECHNOLOGIES AG
  • US7847643B2 patent drawing
  • US7847643B2 patent drawing
  • US7847643B2 patent drawing

AI summary

In an embodiment, a circuit is provided comprising a multi-phase oscillator configured to output a plurality of output signals having the same frequency and different phase offsets. A feedback value is generated based on at least two of said output signals. A reference value is generated based on a reference clock and a predetermined value. The reference value and the feedback value are combined.