Multiphase PLL Circuit for Interference-Robust Phase Locking
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Solution Overview
Problem
Existing Phase Locked Loop (PLL) circuits are sensitive to interference and prone to losing lock, particularly in applications requiring high reliability and multiple antennas and frequency bands, such as cellular communications, where robustness to interference is compromised.
Innovation Solution
A PLL circuit with a digitally controlled oscillator, sample circuit, analog to digital converter, phase estimator, differentiator, accumulator, and loop filter that allows phase detection anywhere on the waveform, enabling unlimited phase detection range and robustness to interference by calculating and accumulating phase differences, thereby generating a control signal for frequency adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If subsampling phase detectors are used to achieve low phase noise with limited power consumption, then phase noise performance is improved, but robustness to interference is sacrificed
Solution Approach 1:
The phase detection function is segmented into multiple independent phase detectors operating at different phases. Instead of using a single subsampling phase detector, the invention employs multiple phase detectors that sample the oscillator output at different phase points, thereby distributing the detection function across multiple channels to improve robustness while maintaining phase noise performance.
Solution Approach 2:
The phase detection system is designed to perform multiple functions simultaneously: it detects phase noise through subsampling while also providing interference robustness through multiphase sampling. The same hardware infrastructure supports both high-performance phase noise measurement and reliable operation under interference conditions.
2Use of energy by moving object
If traditional subsampling phase detectors are used, then power consumption is reduced, but the PLL becomes sensitive to interference and prone to losing lock
Solution Approach 1:
The power-efficient subsampling approach is extended to multiple phases rather than a single detector. By segmenting the detection across multiple phase samples, the system maintains the low power consumption advantage of subsampling while gaining interference robustness through the diversity of phase samples.
Solution Approach 2:
The system changes the sampling parameter by taking measurements at multiple phase offsets rather than a single phase point. This parameter variation allows the system to distinguish between legitimate phase noise and interference, maintaining low power consumption while improving reliability.
Data Source
AI summary
A Phase Locked Loop PLL circuit and method therein for generating multiphase output signals are disclosed. The PLL circuit includes a digitally controlled oscillator, a sample circuit, an analog to digital converter and a digital processing unit. The digital processing unit comprises a phase estimator configured to estimate a phase of the multiphase output signals, a differentiator configured to calculate a phase difference between a current phase and a previous phase, and an accumulator configured to accumulate the phase differences generated by the differentiator. The PLL circuit further comprises a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.