Multiphase PWM Signal Generation for Fine Duty Cycle Control
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Solution Overview
Problem
Existing PWM signal generation methods face limitations in accuracy and resolution due to clock frequency constraints, particularly in high-frequency applications where precise control of duty cycle is necessary to minimize power consumption and noise levels.
Innovation Solution
A PWM signal generator circuit utilizing a multiphase clock generator to produce phase-shifted clock phases, allowing for precise control of switch-on and switch-off durations by combining integer clock periods with fractional periods, thereby enhancing resolution and accuracy of the PWM signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digital implementation using clock signal and counter is used to generate PWM signal, then the circuit implementation is simple, but the accuracy and resolution of the PWM signal is limited by the clock period
Solution Approach 1:
The invention segments the clock period into multiple phases (e.g., 5 phases) that are shifted relative to each other. By selecting different combinations of these phase signals, the circuit can achieve finer resolution PWM control without requiring a higher base clock frequency, thus improving measurement precision while maintaining manageable device complexity.
Solution Approach 2:
The invention dynamically selects and combines different phase-shifted clock signals based on the required PWM duty cycle. This dynamic selection allows the system to achieve variable resolution PWM output, improving adaptability and precision without permanently increasing circuit complexity for all possible resolution levels.
2Measurement precision
If the clock frequency is increased to improve PWM signal resolution, then the accuracy and resolution improve, but the switching losses increase
Solution Approach 1:
Instead of increasing the base clock frequency, the invention segments the existing clock period into multiple phase signals. This allows achieving higher effective resolution (e.g., 12-bit resolution) without increasing the switching frequency, thereby maintaining acceptable switching losses while improving PWM signal resolution.
Solution Approach 2:
The invention uses periodic phase-shifted clock signals with fixed phase relationships. By periodically selecting different phase combinations, the system achieves fine-grained PWM control without requiring continuous high-frequency switching, thus reducing switching losses while maintaining precision.
3Measurement precision
If multiple phase-shifted clock signals are used to improve PWM resolution, then the accuracy and resolution improve, but the device complexity increases
Solution Approach 1:
The invention merges multiple phase-shifted clock signals into a unified PWM generation framework. By combining these signals through logical operations and selective gating, the system achieves high-resolution PWM output without requiring separate complex circuits for each phase, thus reducing overall device complexity while improving precision.
Solution Approach 2:
The phase-shifted clock signal generation circuit serves multiple functions: it provides timing references for PWM generation, enables resolution scaling through phase selection, and supports various duty cycle configurations. This multi-functionality reduces the need for additional dedicated circuits, thereby managing device complexity while improving PWM resolution.
Data Source
AI summary
A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.