Multi-Phase PWM Circuit for PVT-Robust Edge Timing
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Solution Overview
Problem
Existing PWM signal generation circuits suffer from resolution degradation due to PVT variations, especially when using multi-phase clock configurations, leading to edge variations and waveform deterioration, which complicates the circuit design and reduces image resolution in electrophotography applications.
Innovation Solution
A PWM outputting circuit comprising a multi-phase-clock generating circuit, an edge-pulse generating circuit, and an SR latch circuit, which detects rising and falling edges in pattern data to generate robust high-resolution PWM signals, reducing edge variation and maintaining high resolution despite PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multi-phase clock configuration is used to generate high-resolution PWM signals, then the image resolution is improved, but PVT variations cause edge variation and degradation of PWM resolution
Solution Approach 1:
The patent segments the PWM signal generation into multiple independent stages: multi-phase clock generation, parallel data latching, and sequential output. Each stage operates independently with its own timing, which isolates the system from PVT variations and prevents edge variation from propagating through the entire signal path.
Solution Approach 2:
The patent performs preliminary latching of parallel data to multi-phase clocks before the actual PWM output is generated. This preliminary action ensures that all data is captured and stabilized before being transferred to the output register, eliminating the impact of subsequent PVT variations on the already-latched data.
2Ease of manufacture
If common XOR circuits are used for logic operations in PWM generation, then the circuit can be implemented, but the number of gate stages increases causing PVT variation and PWM resolution deterioration
Solution Approach 1:
The patent extracts and eliminates the problematic XOR logic from the PWM generation path. Instead of using XOR circuits for logic operations, the design uses direct parallel-to-serial transfer through latched registers, removing the source of gate-stage-induced PVT variations while maintaining circuit implementability.
Solution Approach 2:
The patent uses replicated register structures that can be easily manufactured using standard cell libraries. These register copies provide the necessary logic functionality without requiring complex XOR gate arrangements, thus maintaining ease of manufacture while improving resolution through reduced gate stages.
3Measurement precision
If narrow pulse width signals indicating phase differences are generated for high resolution, then PWM resolution is increased, but signal quality degrades or disappears due to PVT variations
Solution Approach 1:
The patent uses periodic multi-phase clocks with well-defined periods to drive the parallel-to-serial conversion. This periodic action ensures that even narrow pulse widths are generated at predictable intervals with sufficient margin, preventing signal quality degradation while maintaining high resolution through the regular timing structure.
Data Source
AI summary
This invention provide a PWM outputting circuit that, from pattern data represented by a plurality of bits representing a pulse width, generates a pulse width modulation signal, wherein the circuit comprises a multi-phase-clock generating circuit which generates a multi-phase clock which is a plurality of clocks of mutually different phases; an edge-pulse generating circuit which, from the pattern data that is inputted, detects a bit position of a rising-edge and a bit position of a falling-edge in the pulse width modulation signal, and generates a rising-edge-pulse and a falling-edge-pulse based on the detection; and an SR latch circuit which, by the rising-edge-pulse being inputted to a set terminal and the falling-edge-pulse being inputted to a reset terminal, generates and outputs the pulse width modulation signal.