Multiphase Time Measurement Circuit for High-Resolution PWM Timing

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Solution Overview

Problem

Existing time measurement circuits for PWM signals face limitations in accuracy and resolution due to the clock period, which is inadequate for high-resolution applications such as wireless battery chargers and switching mode power converters, where precise control of duty cycle is necessary to maintain system stability and reduce noise.

Innovation Solution

A time measurement circuit utilizing a multiphase clock generator to produce phase-shifted clock phases, allowing for the determination of a phase value indicative of the time elapsed between a clock signal edge and an asynchronous event, enabling precise measurement of clock cycles and fractions of clock cycles, thereby enhancing the resolution of PWM signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a single-phase clock signal is used for time measurement, then the circuit structure is simple, but the measurement precision is limited by the clock period

Engineering Contradiction:
Improvetime measurement precisionVSAvoidcircuit structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The clock signal is divided into multiple phase-shifted signals (e.g., 4 phases with 90-degree shifts). Each phase captures timing information for a specific time window, allowing the system to measure time elapsed with resolution of 1/n of the clock period. This segmentation of the time measurement function across multiple phases directly resolves the contradiction by improving precision without requiring a proportional increase in overall system complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from single-dimensional time measurement (one clock phase) to multi-dimensional measurement by introducing phase-shifted dimensions. The phase value indicates which time window the asynchronous event fell into, adding a temporal dimension to the measurement. This dimensional expansion enables higher resolution measurements while maintaining the same clock frequency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If the clock period is reduced to improve measurement resolution, then the measurement precision increases, but the circuit operation speed and noise increase

Engineering Contradiction:
ImprovePWM signal resolutionVSAvoidnoise and system instability
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

Instead of reducing the clock period, the invention segments the measurement function across multiple phases of the existing clock signal. This allows achieving fine resolution (1/n of clock period) without changing the clock frequency, thereby avoiding the noise and stability issues associated with high-frequency operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the parameter used for resolution from clock period frequency to phase number. By varying the number of phases (e.g., 4 phases providing 1/4 resolution), the system can adjust measurement precision without altering the clock frequency, thus avoiding the harmful effects of high-frequency operation while maintaining flexible resolution control.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11095291B2Time measurement circuit, system having a PWM signal generator circuit and a time measurement circuit, and corresponding integrated circuit
Publication Date: 2021.08.17 STMICROELECTRONICS SRL
  • US11095291B2 patent drawing
  • US11095291B2 patent drawing
  • US11095291B2 patent drawing

AI summary

A time measurement includes a multiphase clock generator and a phase sampling circuit. The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases, wherein one of the phase shifted clock phases represents a reference clock signal. The phase sampling circuit is configured to generate a phase value indicative of a number of fractions 1/n of the clock period of the clock phases elapsed between an edge of the reference clock signal and an instant when an asynchronous event signal is set. The phase sampling circuit includes first through fourth sub-circuits, which respectively generate or determine first through fourth control signals.