Adjustable Multiphase Ring Oscillator for Precise Sub-Rate Clocking
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Solution Overview
Problem
High-speed serial link receivers face challenges in minimizing area and power consumption for precise clock generation, as traditional scaling methods do not apply to analog serial links, and sub-rate receiver architectures are used to relax sampling latch and clock distribution requirements.
Innovation Solution
A multiphase signal generator with a ring oscillator and adjustable delay stages, allowing for flexible phase relationship adjustment between output phases, which can be adapted to specific transmission channel needs, and a phase locked loop with multiple phase detectors for improved clock generation and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional scaling methods are used for digital logic, then area and power consumption are reduced, but these methods do not apply to analog serial links
Solution Approach 1:
The patent changes the operating parameters of the serial link system by introducing sub-rate reception (receiving at 1/S of data rate) and using a multiphase signal generator to produce S equidistant phases. This allows the analog serial link to operate at lower clock frequencies while maintaining data integrity through phased sampling, making traditional low-power scaling approaches applicable to analog domains.
2Use of energy by moving object
If sub-rate receiver architectures are used to relax sampling latch and clock distribution requirements, then power consumption is reduced, but area and power consumption for precise clock generation remain challenging
Solution Approach 1:
The patent segments the clock generation function into multiple independent phases (S equidistant phases) generated by the multiphase signal generator. Each phase can be independently optimized and distributed to different sampling latches, allowing precise clock generation for each phase while reducing the overall burden on any single clock distribution path and enabling power-efficient sub-rate operation.
Solution Approach 2:
The patent introduces adjustable delay stages in each phase path that can be dynamically controlled to fine-tune the phase relationships. This dynamic adjustment capability allows the system to optimize clock phases for different data rates and channel conditions, maintaining precision while adapting to various operating modes and minimizing power consumption.
3Measurement precision
If an adjustable phase locked loop is used for highly precise clock generation, then clock precision is improved, but area and power consumption increase
Solution Approach 1:
The patent creates a multiphase signal generator that serves multiple functions simultaneously: it generates S equidistant phases for sub-rate sampling, provides adjustable phase shifts for optimization, and works with the phase locked loop for precise clock generation. This multi-functional design eliminates the need for separate dedicated circuits for each function, reducing overall area and power consumption while maintaining high precision.
4Adaptability or versatility
If multiple delay stages are added to adjust phase relationships, then flexibility and adaptability are improved, but device complexity increases
Solution Approach 1:
The patent merges the delay adjustment functionality directly into the phase generation path by placing adjustable delay stages within each phase output path of the multiphase signal generator. This integration allows phase relationship adjustment to be achieved through the existing signal flow structure rather than adding separate complex control circuits, thereby improving flexibility while minimizing increases in device complexity.
Data Source
AI summary
A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.