Multi-Phase Sampler Circuit With Precharge FETs for Low Kickback
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, existing sampling methods face challenges in minimizing energy leakage, known as 'kickback,' which can perturb measurements and affect the accuracy of signal detection.
Innovation Solution
The implementation of a low kickback sampler design that uses pre-charging and discharging FET pairs to generate differential currents and latch output voltages, with a symmetric circuit structure to cancel out clock-related noise and reduce input kickback, along with an offset voltage compensator to further minimize power utilization and noise immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sampling methods are used in high-speed communication systems, then signal detection can be performed, but input kickback energy occurs which perturbs measurements and reduces accuracy
Solution Approach 1:
The sampling circuit is divided into multiple independent FET pairs (first FET pair, second FET pair, third FET pair, fourth FET pair) that operate in parallel. Each FET pair handles specific sampling phases independently, which segments the kickback generation into isolated units that can be controlled and cancelled individually through differential architecture.
Solution Approach 2:
The patent employs differential FET pairs where one FET in each pair acts as a counterweight to the other. The first and second FET pairs generate differential currents that counterbalance each other's kickback effects. Similarly, the third and fourth FET pairs provide counterbalancing action during discharge phases, effectively cancelling input kickback through symmetric opposite actions.
2Productivity
If sampling circuits operate at high speed to meet communication requirements, then data transmission rate increases, but kickback energy and noise increase which affects measurement accuracy
Solution Approach 1:
The sampling circuit operates in periodic phases controlled by clock signals. The first FET pair samples during specific clock phases while the second FET pair operates in complementary phases. This periodic alternating action allows high-speed sampling while maintaining accuracy because each phase is optimized for its specific timing window, and the differential architecture cancels kickback that occurs periodically at each phase transition.
Solution Approach 2:
While the overall architecture is symmetric, individual FET pairs are configured with asymmetric timing and control signals. The first FET pair is controlled by one set of clock phases while the second FET pair is controlled by complementary phases, creating asymmetric operation patterns that distribute kickback events in time and allow for effective cancellation through differential processing.
3Productivity
If multiple sampling phases are implemented to increase data rate, then productivity improves, but device complexity increases
Solution Approach 1:
The FET pairs are designed to perform multiple functions: the first and second FET pairs serve both as sampling switches and as kickback cancellation elements through their differential configuration. The third and fourth FET pairs similarly function as both discharge switches and kickback compensators. This multi-functionality allows the circuit to achieve high sampling rates with multiple phases without proportionally increasing complexity, as each component serves dual purposes.
Solution Approach 2:
The patent merges the sampling function and the kickback cancellation function into a single integrated differential FET pair structure. Rather than having separate sampling circuits and separate kickback compensation circuits, the differential FET pairs inherently provide both functions simultaneously. This merging reduces overall device complexity compared to implementing multiple independent circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces input kickback energy, enhancing the accuracy and reliability of signal measurements while maintaining low power consumption and noise robustness, making it suitable for high-speed communication systems.
Implementation Method 1
pre-charging a corresponding pair of output nodes using a pre-charging field-effect transistor (FET) pair receiving the sampling interval signal, forming a differential output voltage by discharging the corresponding pair of output nodes via a discharging FET pair
Data Source
AI summary
Methods and systems are described for receiving a signal to be sampled and responsively generating, at a pair of common nodes, a differential current representative of the received signal, receiving a plurality of sampling interval signals, each sampling interval signal received at a corresponding sampling phase of a plurality of sampling phases, for each sampling phase, pre-charging a corresponding pair of output nodes using a pre-charging FET pair receiving the sampling interval signal, forming a differential output voltage by discharging the corresponding pair of output nodes via a discharging FET pair connected to the pair of common nodes, the FET pair receiving the sampling interval signal and selectively enabling the differential current to discharge the corresponding pair of output nodes, and latching the differential output voltage.