Multi-Phase Scanning Circuit for Lower TFT Deterioration
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Solution Overview
Problem
Existing scanning circuits in electro-luminescent display devices, particularly those using thin-film transistors (TFTs), suffer from TFT deterioration due to prolonged activation periods, especially in oxide and amorphous silicon TFTs, leading to performance degradation.
Innovation Solution
A scanning circuit configuration utilizing shift registers controlled by multiple phases of clock signals with specific pulse widths and transfer steps, incorporating thin-film transistors of the same conductive type, to output gate signals with extended pulse durations and overlap scanning, reducing TFT activation time and minimizing deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a longer control period is provided for threshold voltage compensation, then data signal writing accuracy is improved, but TFT deterioration is worsened due to prolonged activation
Solution Approach 1:
The control period is segmented into multiple sub-periods with different activation levels. During the first sub-period, the scanning circuit is fully activated for threshold voltage compensation. During subsequent sub-periods, the scanning circuit is deactivated or reduced to minimal activity, allowing threshold voltage stabilization without continuous TFT activation. This segmentation enables accurate data writing while reducing cumulative TFT stress.
Solution Approach 2:
The patent implements periodic activation patterns where the scanning circuit is activated in pulses rather than continuously. The control signal includes an activation period for threshold compensation followed by a non-activation period. This periodic action allows the TFT to undergo threshold voltage compensation when needed while remaining inactive during other periods, thereby reducing deterioration from prolonged activation.
2Stability of the object's composition
If TFTs are kept activated for extended periods to ensure proper compensation, then threshold voltage stability is improved, but device lifetime is reduced
Solution Approach 1:
The patent performs threshold voltage compensation in advance during a dedicated first period before the main data writing operation. By completing the compensation action preliminarily, the system establishes stable threshold voltages without requiring continuous TFT activation throughout the entire display cycle, thereby extending device lifetime while ensuring threshold stability.
Solution Approach 2:
The patent extracts the threshold voltage compensation function from the continuous operation of the scanning circuit. By separating compensation into a distinct initial phase and then deactivating the scanning circuit, the system achieves threshold voltage stabilization without maintaining continuous TFT activation, thus preserving device lifetime.
3Measurement precision
If multiple phase clock signals are used with specific pulse widths, then scanning precision is improved, but circuit complexity increases
Solution Approach 1:
The patent employs multiple phase clock signals where each clock phase serves multiple functions: timing control for data writing, activation/deactivation control for threshold compensation, and coordination with pixel circuit operations. By making the clock system multi-functional, the patent achieves precise scanning control without proportionally increasing circuit complexity, as the same clock infrastructure handles multiple control tasks.
Data Source
AI summary
Shift registers output high-level pulses each having a length of two or more horizontal periods one after another with a transfer step of one horizontal period. The shift register is controlled by a first clock signal and a second clock signal in m phases of clock signals. The shift register includes a high-level output thin-film transistor, a low-level output thin-film transistor and a buffer thin-film transistor. The buffer thin-film transistor receives a control signal having a pulse width and a cycle same as the first clock signal in a period where an output terminal is outputting a low-level potential. High-duties of the first clock signal and the second clock signal are expressed as PW/mH, where PW represents pulse widths of the first clock signal and the second clock signal and H represents one horizontal period. On-duties of all the thin-film transistors are not more than PW/mH.