Multi-Phase Signal Generator Using Duty-Ratio Control for Wide Frequencies
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Solution Overview
Problem
Conventional quadrature phase signal generators, implemented using delay locked loop (DLL) circuits, occupy large areas and are complex, limiting their ability to operate in a wide frequency range without deteriorating signal characteristics.
Innovation Solution
A multi-phase signal generator with a duty control buffer, edge combiners, and a control voltage generator that adjusts duty ratios of differential output signals based on control voltage and digital control codes, allowing for the generation of multi-phase signals with a 90-degree phase difference without increasing circuit complexity or area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DLL circuit with VCDL or delay elements connected in series is used to generate quadrature phase signals, then the signal generation function is achieved, but the circuit design becomes complicated and the circuit occupies a large area
Solution Approach 1:
The circuit is divided into separate functional modules: a duty control buffer for generating differential output signals with adjustable duty ratios, and edge combiners for combining edges to produce multi-phase output signals. This modular segmentation simplifies the overall circuit design while maintaining the quadrature phase signal generation function.
Solution Approach 2:
The invention extracts and eliminates the complex VCDL and series-connected delay elements from the circuit. Instead, it uses a duty control buffer with edge combiners, removing the problematic components that caused circuit complexity and large area occupation while preserving the essential signal generation capability.
2Reliability
If a DLL circuit with VCDL or delay elements connected in series is used to generate quadrature phase signals, then the signal generation function is achieved, but the circuit occupies a large area
Solution Approach 1:
By segmenting the circuit into compact functional modules (duty control buffer and edge combiners), the overall circuit area is reduced. Each module performs a specific function with minimal space requirements, avoiding the large area occupation of traditional VCDL and series delay element configurations.
Solution Approach 2:
The invention removes the area-consuming VCDL and series delay elements from the circuit design. The replacement architecture using duty control buffer and edge combiners occupies significantly less chip area while maintaining the quadrature phase signal generation function.
3Reliability
If a conventional DLL circuit is used, then quadrature phase signal generation is achieved, but the circuit cannot operate in a wide frequency range without deteriorating signal characteristics
Solution Approach 1:
The duty control buffer incorporates adjustable duty ratios that can be dynamically controlled to optimize performance across different frequency ranges. This dynamic adaptability allows the circuit to maintain signal characteristics throughout a wide frequency range, unlike fixed-architecture DLL circuits.
Solution Approach 2:
The invention changes key circuit parameters (duty ratios of differential output signals) to adapt to different operating frequencies. By adjusting these parameters, the circuit maintains optimal signal characteristics across a wide frequency range, providing both reliability and frequency versatility.
Data Source
AI summary
A multi-phase signal generator may include a duty control buffer configured to receive a first differential input signal and a second differential input signal, and generate a first differential output signal and a second differential output signal having variable duty ratios based on a control voltage, a first edge combiner configured to generate a first pulse signal based on first edges of the respective first and second differential output signals, a second edge combiner configured to generate a second pulse signal based on second edges of the respective first and second differential output signals, and a control voltage generator configured to generate the control voltage in response to a logic signal obtained by performing a logic operation on the first and second pulse signals.