Multi-Phase Frequency Synthesizer for Low-Jitter Clock Generation
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Solution Overview
Problem
Conventional frequency synthesizers suffer from jitter and cumulative inaccuracy due to limited phases and self-clocking state machines, limiting their applications.
Innovation Solution
A digital frequency synthesizer using a multi-phase oscillator with a state machine that selects phases to prevent error accumulation, combined with a retiming network and clock construction circuitry to achieve low jitter and accurate frequency synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a limited number of phases are used in the frequency synthesizer, then the device complexity is reduced, but the jitter increases due to phase selection errors
Solution Approach 1:
The patent pre-calculates and stores the optimal phase selection sequence in a lookup table before operation. This preliminary action allows the synthesizer to directly retrieve the correct phase sequence without real-time calculation, eliminating jitter while maintaining low complexity with only 4 phases.
Solution Approach 2:
The patent introduces a lookup table as an intermediary between the phase selector and the output. This lookup table stores pre-computed phase sequences that mediate between the limited 4 phases and the desired high-frequency output, resolving the jitter issue without requiring more phases.
2Device complexity
If a self-clocking state machine is used for phase selection, then the device complexity is reduced, but cumulative inaccuracy occurs due to error accumulation
Solution Approach 1:
The patent introduces an external clock signal as an intermediary to replace the self-clocking mechanism. This external clock acts as a stable reference that prevents error accumulation, while the lookup table translates this stable clocking into the required phase selection sequence without introducing inaccuracy.
Solution Approach 2:
The patent uses the external clock signal as a feedback reference to synchronize the phase selection process. By comparing the desired output frequency with the stable external clock, the system maintains frequency accuracy without cumulative errors while keeping the state machine simple.
3Reliability
If more phases are used to reduce jitter, then the jitter decreases, but the device complexity increases
Solution Approach 1:
Instead of adding more phases, the patent pre-calculates the optimal usage sequence of the 4 available phases and stores it in a lookup table. This preliminary computation eliminates the need for additional phases while achieving the same jitter reduction效果, maintaining low device complexity.
Solution Approach 2:
The patent creates a virtual expansion of the phase space by using a lookup table that stores pre-computed phase sequences. This copying approach allows the system to achieve the performance of a high-phase system using only 4 physical phases, avoiding the complexity increase.
4Device complexity
If self-clocking is used in the state machine, then the circuitry is simplified, but cumulative inaccuracy limits the application range
Solution Approach 1:
The patent introduces an external clock signal as an intermediary reference that enables the simplified state machine to achieve high accuracy. This external clock mediator allows the system to maintain simple circuitry while expanding its application range to frequency-critical applications.
Solution Approach 2:
The external clock provides a stable feedback reference that prevents error accumulation in the state machine. This feedback mechanism allows the simplified circuitry to maintain frequency accuracy across a wider range of applications without limiting the system's versatility.
Data Source
AI summary
A system and method for synthesizing a frequency using a multi-phase oscillator. A state machine operating on one of the phases of the oscillator computes, based on a pair of input integers, a phase select vector that indicates when a particular phase of the multi-phase oscillator should be selected when a transition of the waveform of the output frequency is needed. The phase select vector is then re-timed to form a retimed phase vector so that each phase select signal is in phase with signal it is designed to select. The signals in the retimed phase vector then can be combined to create the output frequency directly or can be used to select the corresponding phase of the multi-phase oscillator, if more accuracy is desired. In one embodiment, the multi-phase oscillator is a rotary traveling wave oscillator which provides highly accurate multiple phases.