Multiphase TDC Circuit for Wider Range With Lower Power
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Solution Overview
Problem
There is a trade-off between resolution, range, and power consumption in Time to Digital Converters (TDCs) used in digital Phase Locked Loops (PLLs), where high resolution requires more delay cells, increasing power consumption and in-band phase noise, and reducing the detection range is challenging while maintaining performance.
Innovation Solution
A TDC arrangement that uses a multiphase signal with N phases, where phase detectors compare each phase with a reference signal, and a logic circuit selects the closest phase, reducing the required detection range by a factor of N, allowing for a simpler circuit with lower power consumption and extended detection range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the TDC detection range is increased to cover at least one clock cycle of the DCO signal, then the range requirement is satisfied, but the delay line length must be increased which leads to higher power consumption
Solution Approach 1:
The patent divides the delay line into multiple segments, each handled by a separate TDC instance. Instead of using one long delay line that consumes high power, the system uses several shorter delay lines working in parallel or sequentially, reducing the power consumption of each individual TDC while collectively covering the full detection range required by the PLL.
2Measurement precision
If the TDC resolution is increased to reduce in-band PLL phase noise, then the phase noise performance is improved, but the number of delay cells must be increased which increases power consumption
Solution Approach 1:
The patent achieves high resolution by segmenting the measurement function across multiple TDC instances rather than relying on a single high-resolution TDC. Each TDC instance uses a shorter delay line with fewer cells, reducing power consumption, while the collective measurement capability of all instances provides the required high resolution for low phase noise performance.
3Length of moving object
If the number of delay cells is increased to satisfy the range requirement, then the detection range is sufficient, but the in-band phase noise increases
Solution Approach 1:
The patent reduces in-band phase noise by segmenting the delay line into multiple shorter segments, each processed by a separate TDC instance. This segmentation prevents the phase noise accumulation that occurs in long single delay lines, as each short segment contributes less phase noise, and the overall system achieves the required detection range through coordinated operation of multiple instances.
4Measurement precision
If a high resolution TDC is implemented with many delay cells, then the resolution requirement is met, but the device complexity increases
Solution Approach 1:
The patent reduces device complexity by segmenting the high-resolution measurement function across multiple simpler TDC instances. Each instance uses a manageable number of delay cells, avoiding the complexity of implementing a single TDC with a very large number of cells. The segmented architecture simplifies timing closure, reduces interconnection complexity, and makes the design more implementable in standard CMOS processes.
Data Source
AI summary
A Time to Digital Converter (TDC) arrangement includes a first delay circuit configured to receive a signal with N phases; a set of phase detectors configured to compare each phase of the signal with a reference signal; a logic circuit configured to receive output signals from the set of phase detectors and detect which phase signal that is the closest signal leading or lagging the reference signal; a first multiplexer configured to receive outputs from the first delay circuit and the logic circuit; a second delay circuit configured to delay the reference signal; a TDC configured to receive output signals from the first multiplexer and the second delay circuit; an adder configured to sum outputs from the logic circuit and the TDC and generate an output signal of the TDC arrangement.