Multiphase TDC Architecture for Wider Range With Lower Power
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Solution Overview
Problem
There is a trade-off between resolution, range, and power consumption in Time to Digital Converters (TDCs) used in digital Phase Locked Loops (PLLs), where high resolution requires more delay cells, increasing power consumption and in-band phase noise, and reducing the detection range is challenging while maintaining performance.
Innovation Solution
A TDC arrangement that uses a multiphase signal with N phases, where phase detectors compare each phase with a reference signal, a logic circuit determines the closest phase, and a multiplexer selects this phase to reduce the detection range by a factor of N, allowing for reduced power consumption and increased detection range with a simpler architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the TDC detection range is increased to cover at least one clock cycle of the DCO signal, then the range requirement is satisfied, but the delay line length must be increased which leads to higher power consumption
Solution Approach 1:
The detection range is segmented into multiple phases (N phases) of the DCO signal. Instead of using a single long delay line to cover the entire clock cycle, the system divides the cycle into N segments, each covered by a separate phase detector comparing a specific phase with the reference signal. This segmentation allows each delay line to be shorter while collectively covering the full range.
Solution Approach 2:
The patent transitions from a one-dimensional approach (single delay line covering entire range) to a two-dimensional approach (multiple phases in time domain combined with multiple parallel comparison paths). By utilizing the phase dimension of the periodic signal, the system achieves extended detection range without proportionally increasing delay line length.
2Measurement precision
If the TDC resolution is increased to reduce in-band PLL phase noise, then the phase noise performance is improved, but more delay cells are required which increases power consumption and device complexity
Solution Approach 1:
The resolution requirement is distributed across multiple phase detectors operating in parallel. Each detector handles a specific phase segment, allowing the use of fewer delay cells per detector while maintaining overall high resolution through the combined output of all N phase detectors.
Solution Approach 2:
Each phase detector operates with a reduced delay line length compared to what would be needed for full-range high-resolution detection. The system accepts that individual detectors have limited resolution capability, but the collective output of all N detectors achieves the required overall resolution, using less total hardware than a single full-range detector.
Data Source
AI summary
A Time to Digital Converter (TDC) arrangement includes a first delay circuit configured to receive a signal with N phases; a set of phase detectors configured to compare each phase of the signal with a reference signal; a logic circuit configured to receive output signals from the set of phase detectors and detect which phase signal that is the closest signal leading or lagging the reference signal; a first multiplexer configured to receive outputs from the first delay circuit and the logic circuit; a second delay circuit configured to delay the reference signal; a TDC configured to receive output signals from the first multiplexer and the second delay circuit; an adder configured to sum outputs from the logic circuit and the TDC and generate an output signal of the TDC arrangement.