Multi-Phase Time-to-Digital Converter for Higher Resolution
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Solution Overview
Problem
Time-to-digital converters face a challenge in improving resolution without increasing circuit scale, as existing solutions require multiple delay elements, leading to increased complexity.
Innovation Solution
A time-to-digital converter design that includes an input terminal for two signals, a phase information generator with inverter elements, multiple D-type flip-flop circuits, and delay elements, allowing for improved resolution without increasing circuit complexity by using flip-flop groups and phase information generators to calculate time intervals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay elements are used in each delay string to improve resolution, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the delay function and phase sampling function into a single integrated structure. The delay element provides a fixed delay time, while multiple D-type flip-flops with different clock phases simultaneously sample the signal at different time points within that delay period. This combination achieves multiple measurement points without requiring multiple separate delay elements, thereby improving resolution while controlling circuit complexity.
Solution Approach 2:
The patent introduces dynamic phase sampling by using multiple clock signals with different phases to control the D-type flip-flops. Instead of using static delay elements for each measurement point, the system dynamically samples the delayed signal at multiple phase points throughout the delay period. This dynamic approach allows the same delay element to serve multiple measurement functions, reducing the overall circuit scale while maintaining high resolution.
2Measurement precision
If the gate lengths of transistors are shortened to reduce resolution, then measurement precision is improved, but manufacturing precision requirements increase
Solution Approach 1:
Instead of changing the physical dimensions of transistors (gate length) to improve resolution, the patent changes the temporal parameters of the system by introducing multiple clock phases with different time offsets. This allows resolution improvement through timing differentiation rather than dimensional reduction, avoiding the need for finer transistor fabrication while achieving the same resolution enhancement.
3Measurement precision
If two delay strings with multiple delay elements are used to achieve 1/2τ delay, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the delay period into multiple phase intervals by using multi-phase clock signals. Instead of creating multiple physical delay strings, the system takes a single delay element and segments its time domain into multiple sampling intervals using flip-flops triggered by different clock phases. This temporal segmentation achieves the equivalent of multiple delay strings without the corresponding increase in physical circuit scale.
Data Source
AI summary
In a time-to-digital converter, a digital signal outputted by a phase information generator is inputted to each of the D terminals of first through Nth (N is a natural number equal to or greater than 2) D-type flip-flop circuits in a first flip-flop group, each of the D terminals is connected to one end of a first delay element, the C terminal of the first D-type flip-flop circuit is connected to another end of the first delay element, the other end of the first delay element is connected to an input terminal, and, when N, the number of flip-flop circuits in the first flip-flop group, is equal to or greater than 3, for each J a natural number from 2 to N−1, C terminal of the (J+1)th D-type flip-flop circuit is connected to one end of the Jth delay element and one end of the (J−1)th delay element is connected to the other end of the Jth delay element.