Multiphase Gated VCO Clock Recovery for Burst-Mode NRZ and PWM
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Solution Overview
Problem
Conventional NRZ data recovery techniques face challenges in generating high-frequency sampling clocks, leading to increased power consumption and circuit complexity, especially when dealing with high data rates and burst mode communications, where existing methods require significant circuit blocks and can introduce timing offsets due to non-uniform phase differences in voltage-controlled delay elements.
Innovation Solution
A gated voltage-controlled oscillator clock data recovery circuit with a balanced load and a four-stage multiphase clock generator, which includes a frequency tracking phase-lock loop oscillator and a replica voltage-controlled oscillator, allowing for stable, accurate, and reduced power NRZ recovery, as well as multi-mode recovery for both NRZ and pulse width modulated data using common hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a locally generated sampling clock at NRZ bit rate is used, then data recovery is achieved, but power consumption increases and circuit complexity increases at high frequencies
Solution Approach 1:
The patent divides the sampling process into multiple phases by generating an N-phase sampling clock from a lower frequency 1/N rate clock. This segmentation allows sampling to occur at multiple time points within each bit period, enabling reliable data recovery at lower clock frequencies and thereby reducing power consumption compared to using a single high-frequency clock.
Solution Approach 2:
The patent employs a voltage-controlled delay element that dynamically adjusts its delay characteristic based on control voltage. This dynamic adjustment allows the N-phase sampling clock to be generated with uniform phase differences despite variations in operating conditions, maintaining reliable data recovery while operating at reduced power levels.
2Speed
If conventional N-phase sampling clock generation using voltage-controlled delay elements is used, then sampling clock is generated, but non-uniform phase differences cause timing offsets
Solution Approach 1:
The patent incorporates feedback mechanisms where the generated N-phase sampling clock is monitored and the control voltage to the voltage-controlled delay element is adjusted based on detected phase uniformity. This feedback loop ensures that uniform phase differences are maintained, eliminating timing offsets while preserving fast sampling clock generation.
Solution Approach 2:
The patent changes the operating parameters of the voltage-controlled delay element by adjusting its control voltage to optimize delay characteristics. By dynamically tuning the delay parameter, the system achieves uniform phase differences across all N phases, resolving the timing offset issue while maintaining high-speed operation.
3Manufacturing precision
If compensation circuitry is added to correct phase non-uniformity, then timing offset is reduced, but device complexity increases
Solution Approach 1:
The patent designs the voltage-controlled delay element to serve multiple functions: it generates the N-phase sampling clock, provides phase uniformity through its controllable delay characteristic, and enables timing accuracy adjustment. This multi-functionality reduces the need for separate compensation circuits, maintaining timing accuracy while minimizing device complexity.
4Productivity
If high data rate NRZ signaling is used, then bandwidth efficiency is improved, but sampling clock generation becomes more difficult
Solution Approach 1:
The patent segments the high-frequency sampling clock generation into multiple lower-frequency phases. By generating an N-phase sampling clock from a 1/N rate clock, the system achieves high data rate sampling without requiring a single high-frequency clock generator, thereby reducing device complexity while maintaining high productivity.
Data Source
AI summary
A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.