Multiplanar Capacitor Using Ring Trench for High Density
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Solution Overview
Problem
Existing semiconductor-on-insulator (SOI) CMOS technologies face challenges in achieving high-capacitance capacitors without increasing process complexity or cost, particularly in high-frequency integrated circuits, as conventional methods either occupy large surface areas or require costly and time-consuming deep trench processing steps.
Innovation Solution
A multiplanar capacitor design using a silicon-on-insulator substrate with a ring-shaped trench filled with conductive material, forming a cavity with a capacitor dielectric on exposed semiconductor surfaces, and utilizing a doped top semiconductor portion and handle substrate as electrodes, which can be manufactured with minimal additional processing steps, compatible with conventional CMOS processing sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar capacitors are used to increase capacitance by increasing area, then capacitance is improved, but chip area occupation increases resulting in low device density
Solution Approach 1:
The patent transitions from a two-dimensional planar capacitor to a three-dimensional multiplanar capacitor structure. The capacitor utilizes multiple horizontal planes (first planar surface, second planar surface) at different elevations, connected by vertical sidewalls. This dimensional transition allows the capacitor to achieve higher capacitance by utilizing vertical space and multiple surfaces, thereby reducing the footprint area occupation while maintaining or increasing capacitance values.
2Quantity of substance
If deep trench capacitors are used to achieve high capacitance at high areal density, then capacitance and areal density are improved, but processing complexity and cost increase significantly
Solution Approach 1:
The multiplanar capacitor structure is designed to be compatible with standard CMOS fabrication processes. The capacitor can be formed using conventional process steps such as deposition, etching, and doping that are already part of the CMOS manufacturing sequence. The structure serves multiple functions: it provides high capacitance, maintains compatibility with existing CMOS processes, and can be integrated alongside logic devices without requiring separate dedicated processing lines or specialized equipment.
Solution Approach 2:
The capacitor is divided into multiple planar surfaces (first planar surface, second planar surface) separated by an insulating layer, with each surface contributing to the total capacitance. This segmentation allows the capacitor to achieve high areal density by utilizing multiple active surfaces within a compact footprint, while each segment can be formed using standard process steps that are already part of the CMOS fabrication sequence.
3Quantity of substance
If deep trench capacitors are used to achieve high capacitance, then capacitance is improved, but total processing time increases resulting in increased time-to-market
Solution Approach 1:
The formation of the multiplanar capacitor is merged with the existing CMOS fabrication sequence. The capacitor structure is built using process steps that are already scheduled in the standard manufacturing flow, such as depositing insulating layers, forming conductive plugs, and performing doping operations. By merging capacitor formation with these existing steps rather than adding separate dedicated processing stages, the total processing time is minimized while still achieving the desired high capacitance values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-capacitance capacitors with improved areal density and reduced processing complexity and cost, suitable for high-frequency integrated circuits, while maintaining compatibility with existing CMOS processing sequences.
Implementation Method 1
A multiplanar capacitor design using a silicon-on-insulator substrate with a ring-shaped trench filled with conductive material, forming a cavity with a capacitor dielectric on exposed semiconductor surfaces, and utilizing a doped top semiconductor portion and handle substrate as electrodes
Data Source
AI summary
An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.