Multiplane Cache Read Latch Transfer with Predictive Timing
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Solution Overview
Problem
Current memory systems introduce wait times between data transfers due to delay in moving data between buffer and gateway latches, which hampers faster data transfers and reduces throughput, especially in multi-plane operations.
Innovation Solution
Implementing predictive transfer techniques where a counter tracks data quantity for the last plane, initiating the wait time before receiving the next cache command, thereby reducing the overall wait time by overlapping data transfer with the command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between buffer and gateway latches using traditional timing methods, then data integrity is maintained, but wait time increases and throughput decreases
Solution Approach 1:
The patent initiates the data transfer from buffer latch to gateway latch before the cache command is fully received by starting the transfer at the beginning of the command rather than waiting until the command is complete. This preliminary action overlaps the transfer operation with the command processing, reducing the overall wait time and improving throughput while maintaining data integrity through predictive timing calculations.
2Reliability
If wait time is introduced between data transfers to ensure proper latching, then data transfer reliability is improved, but overall transfer speed decreases
Solution Approach 1:
The system performs preliminary timing calculations and initiates data transfer before the cache command completion, overlapping the transfer operation with command processing. This approach maintains reliability by ensuring proper latching timing while improving speed by eliminating idle wait periods.
Solution Approach 2:
The patent enables continuous data transfer operations by overlapping the buffer-to-gateway latch transfer with the cache command processing. Instead of having sequential operations with idle gaps, the system maintains continuous useful action where data transfer proceeds concurrently with command handling, improving overall throughput while maintaining transfer integrity.
Data Source
AI summary
Methods, systems, and devices for predictive transfer NAND data register in multiplane cache read are described. A memory device may obtain, from memory after transferring a first set of data from a first set of latches to a second set of latches, a second set of data, where obtaining the second set of data includes loading the second set of data into the first set of latches. The memory device may initialize a counter based on receiving a quantity of commands and may transmit the first set of data from the second set of latches. The memory device may update the counter based on a quantity of the first set of data transmitted subsequent to initializing the counter and may transfer the second set of data from the first set of latches to the second set of latches based on the counter satisfying a threshold.