Multi-Plane Memory Parallel Read Access for Faster Boot Recovery
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Solution Overview
Problem
Existing memory sub-systems face significant latency issues during bootup due to the inefficiency in identifying the last written page after a power loss event, particularly in multi-plane memory devices, which can exceed permissible quality of service requirements.
Innovation Solution
Implementing independent parallel plane access in multi-plane memory devices, where simultaneous read operations are performed on different pages of multiple planes to strategically narrow down the search for the last written page, reducing the number of iterations required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional binary search methods are used to identify the last written page after power loss, then the search process is simple to implement, but bootup latency becomes excessively long
Solution Approach 1:
The memory device is divided into multiple independent planes, each capable of parallel read operations. By segmenting the search process across multiple planes simultaneously, the patent reduces the total time required to identify the last written page compared to sequential binary search methods
Solution Approach 2:
The patent transitions from a one-dimensional sequential binary search approach to a multi-dimensional parallel search by utilizing multiple memory planes. This dimensional expansion allows simultaneous read operations across different planes, significantly reducing bootup latency
2Ease of operation
If multiple read operations are performed sequentially to identify the last written page, then the implementation is straightforward, but the number of iterations required increases bootup latency
Solution Approach 1:
The patent performs preliminary read operations on multiple planes simultaneously to gather information about the last written page location. By conducting these preliminary actions in parallel rather than sequentially, the system reduces the total iteration count and bootup time while maintaining implementation feasibility
3Quantity of substance
If the memory device uses multiple planes for increased storage capacity, then storage density improves, but identifying the last written page becomes more complex and time-consuming
Solution Approach 1:
By segmenting the memory device into multiple independent planes with separate read paths, the patent enables parallel identification of the last written page across all planes. This segmentation approach maintains high storage capacity while reducing the time penalty that would otherwise result from searching through multiple planes sequentially
Data Source
AI summary
A memory sub-system includes a memory device comprising a memory array comprising a plurality of planes a processing device configured to detect a boot process of the system subsequent to an occurrence of a power loss event, and initiate a series of multi-plane read operations to identify a last written page of the memory device, wherein the last written page was programmed prior to the occurrence of the power loss event, and wherein at least a portion of the memory device remains unprogrammed.