Multi-Plane Memory FIFO Buffering for Faster Sequential Readout
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Solution Overview
Problem
The challenge of improving input/output (I/O) efficiency in memory systems with multiple planes is exacerbated by the delay time when transmitting and receiving signals respectively corresponding to the command-address signals for the plurality of planes in memory devices, particularly due to the separate command of separate command and address signals for the command-address signals respectively corresponding to the plurality of planes.
Innovation Solution
A memory device and controller system that includes a memory cell array with multiple planes, first-in-first-out (FIFO) memories, and a second FIFO memory to store and output data based on an initial command-address, allowing for improved I/O efficiency by reducing delay times through the sequential read operation of data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate command-address signals are transmitted for each plane according to SCA protocol, then data can be read from multiple planes, but delay time increases due to sequential signal transmission
Solution Approach 1:
The patent applies preliminary action by transmitting a single initial command-address signal that pre-configures the memory device to read data from multiple planes. The memory device internally prepares and buffers data from all specified planes using this initial command, eliminating the need for subsequent separate command-address signals for each plane. This preliminary configuration reduces the number of signal transmission cycles and minimizes delay time while maintaining the ability to read from multiple planes.
2Productivity
If multiple planes are read sequentially using separate command-address signals, then data from each plane can be retrieved, but I/O efficiency deteriorates due to repeated signal transmission overhead
Solution Approach 1:
The patent merges multiple separate command-address signal transmissions into a single initial command-address signal. Instead of sending individual commands for each plane (Plane 1 command, Plane 2 command, etc.), the system transmits one consolidated initial command-address that specifies all target planes. The memory device internally handles the distribution and coordination of data retrieval from multiple planes based on this single command, thereby reducing signal transmission complexity while preserving multi-plane data retrieval capability.
Data Source
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AI summary
A memory device includes a memory cell array including a plurality of planes, a plurality of first FIFO memories respectively corresponding to the plurality of planes and configured to store at least some pieces of data stored in the plurality of planes, and a second FIFO memory configured to load at least some pieces of data stored in at least one of the plurality of first FIFO memories according to a plane order in which the data stored in the plurality of planes is output, wherein the memory device is configured to store the data stored in each of the plurality of planes in a corresponding first FIFO memory of the plurality of first FIFO memories, respectively, based on an initial command-address provided from a memory controller.