Multi-Plane Memory Serial Encoding to Ease Signal Routing
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Solution Overview
Problem
Efficient routing of communication signals between logic circuits and plane-specific control circuits in multi-plane memory systems is challenging due to the need for numerous conductive connections, which can lead to congestion and limited space for peripheral circuitry.
Innovation Solution
Implementing serial encoder and decoder circuits to convert parallel signals to serial format for communication, reducing the number of conductive connections required and simplifying routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel communication channels are used between logic circuits and plane-specific control circuits, then communication speed is improved, but the number of conductive connections increases leading to routing congestion
Solution Approach 1:
The patent transitions from parallel communication (multiple simultaneous channels) to serial communication (single sequential channel), effectively changing the dimensional approach to data transmission. This dimensionality change allows maintaining communication functionality while reducing the number of conductive connections from multiple parallel lines to a single serial line, thereby resolving the routing congestion issue.
Solution Approach 2:
The patent changes the communication mode parameter from parallel to serial, and adjusts the clock frequency parameter to compensate for the serial transmission speed. By increasing the clock frequency in the serial interface, the patent maintains effective communication speed while reducing conductive connections, thus resolving the contradiction between communication speed and routing congestion.
2Quantity of substance
If parallel communication channels are used, then data transmission capacity is improved, but the space available for peripheral circuitry is reduced
Solution Approach 1:
The patent employs serial communication which changes the data transmission approach from spatial parallelism to temporal sequencing. This allows the same data transmission capacity to be achieved through time-multiplexed serial transmission rather than space-multiplexed parallel transmission, thereby freeing up die area for peripheral circuitry while maintaining data transmission capability.
Solution Approach 2:
The serial communication interface uses periodic clock cycles to transmit data bits sequentially. By organizing data transmission into periodic time slots and using double data rate (DDR) techniques where applicable, the patent maintains effective data transmission capacity through temporal multiplexing, reducing the need for multiple simultaneous conductive connections and freeing up space for peripheral circuits.
3Device complexity
If the number of conductive connections is reduced, then routing is simplified, but communication bandwidth is decreased
Solution Approach 1:
The patent compensates for the reduced communication bandwidth inherent in serial transmission by increasing the clock frequency parameter. By operating the serial interface at higher frequencies and utilizing double data rate (DDR) techniques that transmit data on both rising and falling edges of the clock signal, the patent effectively maintains or even improves communication bandwidth while enjoying the routing simplicity benefits of reduced conductive connections.
Data Source
AI summary
An apparatus includes control circuits configured to connect to a plurality of planes of a nonvolatile memory array. The control circuits are configured to convert a plurality of parallel signals to a plurality of serial signals, send subsets of the plurality of serial signals to respective control circuits for each plane of the plurality of planes and convert each subset of the plurality of serial signals to corresponding parallel signals for each plane.