Multi-Plane Memory Trim Registers for Plane-Specific Voltage Shifts
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Solution Overview
Problem
Existing memory sub-systems face increased bit error rates and latency due to the slow charge loss phenomenon, which causes varying voltage shifts across memory planes during multi-plane operations, leading to inefficient resource consumption and error correction.
Innovation Solution
Allocate distinct sets of registers for each memory plane to store trim values corresponding to individual voltage shifts, allowing the controller to perform multi-plane operations with appropriate trim values, reducing bit error rates and resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multi-plane operations are performed using shared trim values, then device complexity is reduced, but bit error rate increases due to varying voltage shifts across planes
Solution Approach 1:
The patent segments the trim value storage by allocating distinct register sets to each memory plane. Each plane's trim register set stores plane-specific trim values that compensate for that plane's unique voltage shifts, thereby reducing bit error rates while maintaining manageable complexity through systematic organization
Solution Approach 2:
The patent applies local quality by using plane-specific trim values stored in dedicated registers for each plane. This allows each plane to have customized trim values tailored to its specific voltage characteristics, improving reliability without requiring a complete system redesign
2Reliability
If plane-specific trim values are used, then bit error rate decreases, but device complexity increases due to multiple register sets
Solution Approach 1:
The patent organizes multiple trim register sets in a segmented manner, with each set dedicated to a specific plane. This systematic segmentation makes the complexity manageable and allows for efficient address mapping, reducing the practical burden of having multiple registers while maintaining the reliability benefits
Solution Approach 2:
The patent implements a universal trim register structure where each plane has an identical register layout and access mechanism. This multi-functionality allows the same register interface to serve multiple planes, reducing control logic complexity while still providing plane-specific trim values
3Ease of manufacture
If traditional single-set trim values are used for all planes, then manufacturing simplicity is maintained, but latency increases due to additional error correction operations
Solution Approach 1:
The patent performs preliminary action by pre-calculating and storing plane-specific trim values in dedicated registers before multi-plane operations execute. This preparation eliminates the need for runtime error correction, reducing latency while the systematic register allocation keeps manufacturing complexity manageable
Data Source
AI summary
A request is received to perform a multi-plane operation for first data of a first plane and second data of a second plane of a memory device. Responsive to the request, first trim values are retrieved from first trim registers and second trim values are retrieved from second trim registers, the first trim values loaded to the first registers based on a first voltage distribution observed at the first plane during a first time period and the second trim values loaded to the second registers based on a second voltage distribution observed at the second plane during a second time period. The multi-plane operation is performed using at least the first trim values for the first data at the first plane and at least the second trim values for the second data at the second plane.