Multiplate MIM Capacitor Top-Contact Layout for IR Drop Reduction

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Solution Overview

Problem

Conventional metal-insulator-metal (MIM) capacitors provide insufficient decoupling performance for high-performance computing processors, leading to increased IR drop and degraded performance in high-density integrated circuits, especially as technology scales down.

Innovation Solution

The development of a multiplate MIM capacitor configuration with a specific fabrication process that includes forming mesas and depositing multiple metal plates with insulators, allowing for improved electrical coupling and compatibility with standard metal and via processes, enabling enhanced power decoupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional MIM capacitor configuration is used, then manufacturing process is simple, but power decoupling performance is insufficient

Engineering Contradiction:
Improvepower decoupling performanceVSAvoidcapacitor structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The capacitor is divided into multiple plates (first plate, second plate, third plate) arranged in series between two mesas. This segmentation increases the effective capacitance area and improves power decoupling performance without requiring a completely new structure, as each plate can be formed using existing fabrication processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a conventional planar capacitor structure to a three-dimensional multiplate configuration with mesas extending vertically. This dimensional change allows for increased capacitance density by utilizing vertical space, thereby improving decoupling performance within the same footprint area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If technology scales down for high-density circuits, then integration density increases, but IR drop increases and decoupling performance decreases

Engineering Contradiction:
Improveintegration densityVSAvoidpower delivery performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By segmenting the capacitor into multiple plates connected in series, the patent achieves higher effective capacitance in a scaled-down footprint. This allows high-density integration while maintaining sufficient decoupling capacity to address IR drop issues in advanced technology nodes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multiplate structure nests multiple capacitor elements within a compact vertical arrangement between mesas, enabling high integration density. This nested configuration maintains adequate decoupling performance despite reduced lateral dimensions, addressing the IR drop problem in high-density circuits.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Reliability

If multiplate MIM capacitor configuration is implemented, then power decoupling performance improves, but fabrication process complexity increases

Engineering Contradiction:
Improvepower decoupling performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent designs the multiplate MIM capacitor to be compatible with existing standard metal and via fabrication processes. The same deposition and patterning tools used for conventional interconnect structures can form the multiple plates and insulator layers, making the enhanced capacitor structure manufacturable without requiring entirely new fabrication equipment or processes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances power decoupling performance, reduces IR drop, and improves manufacturing compatibility, addressing the limitations of conventional MIM capacitors in high-density integrated circuits.

Implementation Method 1

a first insulator of the MIM capacitor disposed on the first plate; a second insulator of the MIM capacitor disposed on the second plate

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

a first plate of a metal-insulator-metal (MIM) capacitor disposed below the first top contact and electrically coupled to the first top contact

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11973020B2Metal-insulator-metal capacitor with top contact
Publication Date: 2024.04.30 QUALCOMM INC
  • US11973020B2 patent drawing
  • US11973020B2 patent drawing
  • US11973020B2 patent drawing

AI summary

Disclosed are examples of a device and method of fabricating a device including a first top contact, a second top contact, adjacent the first top contact, a first mesa disposed below the first top contact and a second mesa disposed below the second top contact. A first plate of a metal-insulator-metal (MIM) capacitor is disposed below the first top contact and electrically coupled to the first top contact. A first insulator of the MIM capacitor is disposed on the first plate. A second plate of the MIM capacitor is disposed on the first insulator and electrically coupled to the second top contact. A second insulator of the MIM capacitor is disposed on the second plate. A third plate of the MIM capacitor is disposed on the second insulator and electrically coupled to the first top contact.