Multiple Anneal Stress Inducing Layer for Semiconductor Reliability
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Solution Overview
Problem
The introduction of stress into semiconductor devices to enhance electron and hole mobility often results in dislocations within the channel region, leading to transistor shorts, and existing methods to mitigate this issue are costly and time-consuming.
Innovation Solution
A semiconductor device is fabricated using a multiple anneal method, where a stress-inducing layer is subjected to two distinct annealing temperatures, a lower temperature first to reduce dislocations and a higher temperature subsequently to activate dopants, allowing for controlled stress incorporation and reduced defect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single high-temperature anneal process is used to incorporate stress and activate dopants, then device performance is improved through stress introduction, but dislocations are created in the channel region causing transistor shorts
Solution Approach 1:
The single high-temperature anneal process is divided into multiple sequential anneal steps with different temperature profiles. The first anneal step is performed at a lower temperature to incorporate stress into the channel region, while the second anneal step is performed at a higher temperature to activate dopants. This segmentation prevents dislocation formation by avoiding the simultaneous application of both high temperature conditions that cause crystallographic plane shifts.
Solution Approach 2:
The stress incorporation anneal is performed as a preliminary step before the dopant activation anneal. By first introducing stress at a controlled lower temperature, the crystal structure is prepared in a stable state before subsequent high-temperature processing, thereby preventing dislocation formation during the dopant activation phase.
2Object-generated harmful factors
If multiple complex processing steps are used to combat dislocation formation, then dislocation-related shorts are reduced, but manufacturing cost and process time increase
Solution Approach 1:
The patent combines stress incorporation and dopant activation into a coordinated two-step anneal process that is integrated into the existing fabrication flow. Rather than adding separate complex processing steps, the method merges these functions into sequential annealing operations with optimized temperature profiles, achieving dislocation reduction without significantly increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces dislocation formation in the channel region, enhancing the reliability of semiconductor devices while maintaining improved mobility, thus addressing the limitations of single high-temperature anneal processes.
Implementation Method 1
subjecting the stress inducing layer to multiple anneals to reduce the formation of dislocations within a channel region of the semiconductor device. The step of subjecting comprises annealing with a first temperature and then a second temperature
Implementation Method 2
The introduction of the stress can be accomplished by first placing a stress inducing layer, such as a nitride or oxide layer, over completed gate structures. The device is then subjected to an anneal process at temperatures that exceed 1000° C. This not only incorporates stress into the channel region of the transistors, but it is also sufficient to activate the dopants located within source/drains.
Data Source
AI summary
The invention provides a method of fabricating a semiconductor device. In one aspect, the method comprises forming a stress inducing layer over a semiconductor substrate, subjecting the stress inducing layer to a first temperature anneal, and subjecting the semiconductor substrate to a second temperature anneal subsequent to the first temperature anneal, wherein the second temperature anneal is higher than the first temperature anneal.