Multiple Block Memory Complementary Data Path Timing
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Solution Overview
Problem
Managing the timing relationship between global data hold latches and sense amplifiers in multiple block memories is challenging due to varying constraints, leading to timing problems when memory blocks are combined.
Innovation Solution
A multiple block memory with a complementary data path is designed, featuring tri-drivers and data hold latches that precharge and provide data on a data bus based on selective memory block enable signals, allowing for synchronized operation across different memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory blocks are combined to satisfy system requirements, then the memory capacity and functionality are improved, but timing problems arise between global data hold latch and sense amplifier operations
Solution Approach 1:
The patent divides the memory into multiple independent blocks, each with its own sense amplifier and tri-driver circuit. This segmentation allows each block to operate independently with its own timing control, eliminating the timing conflicts that arise when multiple blocks share a global data hold latch. The data bus is segmented into multiple lines, each connected to a specific memory block, enabling simultaneous independent operations.
Solution Approach 2:
The patent implements dynamic timing control for each memory block through separate enable signals that control the tri-driver circuits. Each block's tri-driver can be independently enabled or disabled based on read/write operations, allowing flexible timing adjustment. The global data hold latch is dynamically controlled to latch data only when necessary, adapting to different operational modes of individual blocks.
2Duration of action of stationary object
If a global data hold latch is used to hold data indefinitely, then data retention is improved, but the timing constraints for tri-stating and re-activating the latch become difficult to manage
Solution Approach 1:
Instead of using a single global data hold latch for all memory blocks, the patent segments the data retention function by assigning individual latches to each memory block. Each block's latch is independently controlled by its own enable signal, simplifying timing management. This eliminates the complex coordination required for a single global latch to manage multiple blocks with different timing requirements.
Solution Approach 2:
The patent implements feedback control through enable signals that monitor the operational state of each memory block. When a block is selected for read or write operations, the corresponding enable signal activates the tri-driver and controls the data hold latch timing. This feedback mechanism automatically adjusts latch behavior based on real-time block status, reducing the complexity of manual timing control.
3Ease of operation
If separate circuits are used for precharging and data provision in each memory block, then the timing relationship between operations is simplified, but the circuit complexity increases
Solution Approach 1:
The patent merges the precharging function and data provision function into a single tri-driver circuit for each memory block. This tri-driver circuit can operate in two modes: precharging mode when the enable signal is inactive, and data provision mode when the enable signal is active. By combining these functions into one circuit, the patent reduces overall circuit complexity while maintaining simplified timing control through the unified enable signal.
Solution Approach 2:
The tri-driver circuit in each memory block is designed as a universal component that performs multiple functions: precharging the data bus line when inactive and driving data when active. This multi-functional design eliminates the need for separate precharging circuits for each block, reducing circuit complexity. The same circuit structure handles different operational phases through control signals, making the system more efficient.
Data Source
AI summary
A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to the second memory block. The first circuit is coupled to the data bus and the first sense amplifier. The first circuit switches from precharging the data bus to providing data when the first memory block is selected and is decoupled from the data bus in response to the first memory block being deselected. The second circuit is coupled to the data bus and the second sense amplifier. The second circuit switches from precharging the data bus to providing data when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.