Multiple-Cache Parallel Computing for GPU Block Matching

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Solution Overview

Problem

Current parallel processing methods using GPUs face inefficiencies in handling complex tasks like block matching due to data access overlaps, increased latency, and complexity in handling large images, which require mixed host and device code for recursive processing.

Innovation Solution

A method for multiple-cache parallel computing that executes threads across multiple caches, allowing for thread folding and parallel execution of remaining threads, reducing execution time and optimizing workload distribution across multiple caches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple threads access the same memory address in parallel for block matching, then processing can be parallelized, but data access overlaps occur which increase latency

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the image processing task into multiple independent blocks that can be processed in parallel without memory access conflicts. Each thread block processes a distinct region of the image, eliminating data access overlaps while maintaining parallel processing capability. This segmentation allows full utilization of GPU parallelism without the latency penalties of synchronized memory access.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If the image size increases to cover large areas, then more data can be processed, but the program requires mixed host and device code for recursive processing which increases complexity

Engineering Contradiction:
Improveimage coverage areaVSAvoidprogram complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent handles large images by introducing a block-level parallelism dimension in addition to the pixel-level parallelism. Instead of recursively processing large images through mixed host-device code, the solution processes multiple image blocks simultaneously on the GPU device, each block containing multiple pixels. This dimensional approach allows the entire large image to be processed in a single kernel launch without recursive complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If a simple grid approach is used where each thread processes a single data element, then implementation is simple, but it cannot efficiently handle complex problems involving neighboring pixels and reduction

Engineering Contradiction:
Improveimplementation simplicityVSAvoidcapability to handle complex problems
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent merges the simplicity of the grid approach with the capability to handle complex operations by combining pixel-level parallelism within blocks and block-level parallelism across the image. Each thread within a block can efficiently access neighboring pixels through shared memory, and reduction operations are performed within each block before writing results. This merged approach maintains implementation simplicity while achieving the versatility needed for complex image processing tasks.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9235527B2Multiple-cache parallel reduction and applications
Publication Date: 2016.01.12 JOHNS HOPKINS UNIVERSITY
  • US9235527B2 patent drawing
  • US9235527B2 patent drawing
  • US9235527B2 patent drawing

AI summary

In accordance with an aspect of the present invention, a method and system for parallel computing is provided, that reduces the time necessary for the execution of program function. In order to reduce the time needed to execute aspects of a program, multiple program threads are executed simultaneously, while thread 0 of the program is also executed. These threads are executed simultaneously with the aid of at least one cache of the computing device on which the program is being run. Such a framework reduces wasted computing power and the time necessary to execute aspects of a program.