Multiple-Clock TM-FPGA Mapping for Larger Logic Designs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multiple-clock time-multiplexed field-programmable gate arrays (FPGAs) require extensive user involvement in the design process and do not provide enough hardware resources to implement complex designs efficiently, limiting their usability for general-purpose applications.
Innovation Solution
The development of novel multiple-clock TM-FPGAs that automatically map user designs to programmable logic circuitry without user intervention, utilizing multiple clock signals and context registers to optimize resource usage and reduce die area, allowing for more efficient implementation of larger designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional time-multiplexed FPGAs are used to increase hardware resources, then the apparent hardware resources increase, but the user involvement in the design process increases and the operating speed decreases
Solution Approach 1:
The patent implements automatic mapping of user designs to programmable logic circuitry using an automated tool flow that performs context partitioning, placement, and routing without user intervention. The system self-configures the time-multiplexed architecture by automatically assigning different contexts to different clock cycles, eliminating the need for users to manually manage the complexity of time-multiplexed resource allocation while still providing increased hardware resources.
2Quantity of substance
If conventional time-multiplexed FPGAs are used to increase hardware resources, then the apparent hardware resources increase, but the operating speed decreases
Solution Approach 1:
The patent employs periodic action by assigning different contexts to different clock cycles in a time-multiplexed manner. The programmable logic circuitry is periodically reconfigured across multiple clock cycles to implement different portions of the user design. This allows the system to provide increased hardware resources through time-multiplexing while managing the speed trade-off by optimizing the context switching mechanism and allowing parallel operations within each clock cycle where possible.
Solution Approach 2:
The patent segments the user design into multiple contexts that can be implemented across different clock cycles. Each context represents a portion of the overall design that can be independently mapped to the programmable logic circuitry. This segmentation allows the system to distribute the design across time, providing increased resource capacity while maintaining manageable clock cycle operations and optimizing the balance between resource availability and operating speed.
3Adaptability or versatility
If conventional FPGAs are used to implement complex designs, then the flexibility and programmability are maintained, but the hardware resources are insufficient
Solution Approach 1:
The patent implements continuity of useful action by maintaining the programmable logic circuitry in an active, configurable state across multiple clock cycles through time-multiplexing. Instead of static resource allocation, the system continuously reconfigures the logic circuitry to implement different contexts sequentially. This provides increased effective hardware resources while preserving the flexibility and programmability of FPGAs, as the same physical resources can serve multiple design functions over time.
Data Source
AI summary
A multiple-clock time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry. A plurality of clock signals within the TM-FPGA couple to the programmable logic circuitry. A user's circuit can be mapped to the programmable logic circuitry without the user's intervention in mapping the circuit to the programmable logic circuitry.