Multiple CRC Generation for Code Block Error Detection
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Solution Overview
Problem
In wireless communication systems, particularly in 3GPP LTE, the current method of generating a single 24-bit cyclic redundancy check (CRC) for large transport blocks is inadequate for error detection when multiple code blocks are transmitted, leading to incorrect decoding and unnecessary retransmissions.
Innovation Solution
Calculating multiple cyclic redundancy checks (CRCs) based on subsets or segments of the transport block bits using specific generator polynomials, with the option to interleave or reorder bits for improved error detection and decoding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single 24-bit CRC is generated for the whole transport block, then the hardware complexity is reduced, but the error detection capability deteriorates when multiple code blocks are transmitted
Solution Approach 1:
The patent divides the transport block into multiple code blocks and generates separate CRC checks for each code block in addition to the transport block CRC. This segmentation allows the receiver to identify which specific code block contains errors, improving error detection capability while maintaining reasonable hardware complexity through modular processing.
2Productivity
If multiple code blocks are generated from a large transport block, then parallel processing capability is improved, but the error detection reliability deteriorates with single CRC
Solution Approach 1:
By segmenting the transport block into multiple code blocks with individual CRC checks, the system enables parallel processing of multiple code blocks while maintaining reliable error detection. Each code block can be independently verified, allowing the receiver to correctly identify errors in specific blocks without affecting the processing of other blocks.
3Ease of operation
If the receiver uses a single transport block CRC to verify multiple code blocks, then the checking process is simplified, but the ability to identify specific erroneous blocks is lost
Solution Approach 1:
The patent implements a hierarchical CRC structure where each code block has its own CRC check in addition to the transport block CRC. This allows the receiver to first use code block CRCs to identify which specific blocks contain errors, then use the transport block CRC for overall verification, thereby preserving error location information while maintaining a systematic checking process.
Solution Approach 2:
The patent enables feedback mechanisms where the receiver can identify specific erroneous code blocks through individual CRC checks and request retransmission of only those specific blocks. This selective feedback improves efficiency by avoiding unnecessary retransmission of correctly received blocks while maintaining simple verification procedures.
Data Source
AI summary
Methods and apparatus for generating cyclic redundancy checks (CRCs). In one aspect of the present invention, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits by using a selected cyclic redundancy check generator polynomial, at least one cyclic redundancy check is calculated based upon a first subset of the plurality of bits with a certain bit ordering, and at least another cyclic redundancy check is calculated based upon a second subset of the plurality of bits with a different bit ordering. The second subset of bits may overlap with the first subset of bits. In another aspect, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits by using a plurality of different cyclic redundancy check generator polynomials. A first cyclic redundancy check generator polynomial is used for calculating a first cyclic redundancy check based upon a first plurality of bits, and a second cyclic redundancy check generator polynomial is used for calculating a second cyclic redundancy check based upon a second plurality of bits.