Multiple Data Rate Memory Clock Splitting Circuit
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Solution Overview
Problem
Conventional SRAM memory systems face challenges in implementing multiple memory accesses efficiently while maintaining low power consumption, especially with the increasing demand for larger memories in battery-powered devices, as they typically require controlling both rising and falling edges of the external clock signal, which can be complex for larger clock trees.
Innovation Solution
A multiple data rate memory system that utilizes a clock splitting circuit to generate internal clock pulses from the rising edge of an external clock signal and a multiplexing address latch to facilitate multiple memory accesses, allowing for efficient operation without needing to control both edges of the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional SRAM memory systems control both rising and falling edges of the external clock signal to implement multiple memory accesses, then data transmission rate is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent divides a single external clock cycle into multiple internal clock phases (PHI0, PHI1, PHI2, PHI3) using a clock splitting circuit. This segmentation allows the memory system to perform multiple access operations within one external clock period by utilizing different phases for different operations (e.g., PHI0-PHI1 for read, PHI1-PHI2 for write), thereby achieving multiple data rates without controlling both edges of the external clock signal.
Solution Approach 2:
The clock splitting circuit generates all necessary internal clock phases in advance from a single rising edge of the external clock signal. The phases are pre-synchronized and distributed to different memory access circuits before the actual access operations begin, enabling coordinated multi-phase operations without real-time edge detection and control complexity.
2Productivity
If conventional SRAM memory systems control both rising and falling edges of the external clock signal to implement multiple memory accesses, then data transmission rate is improved, but power consumption increases
Solution Approach 1:
By segmenting the clock signal into multiple phases from a single rising edge, the patent enables multiple memory access operations without requiring continuous clock edge transitions. This reduces the switching activity in clock distribution networks and associated control logic, thereby lowering dynamic power consumption while maintaining high data transmission rates through phased parallel operations.
3Speed
If conventional SRAM memory systems use divided/hierarchical word lines and bit lines to reduce delay and power dissipation, then access speed is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple memory access operations (read, write, read-modify-write) into a unified phased clocking scheme that operates on the existing memory array structure. By merging the control of multiple operations into a single external clock signal that is internally phased, the system achieves the speed benefits of hierarchical structures without adding their structural complexity, as the phased clocking coordinates access across the unified array.
Data Source
AI summary
There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch. The multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse.