Multiple Drain Via MOS Layout for Lower RDS(ON)
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Solution Overview
Problem
MOS chips with vertical designs face challenges in reducing on-resistance (RDS(ON)) due to the need for complex packaging processes and the use of traditional lead frames, which hinder further improvements in conductivity.
Innovation Solution
A metal oxide semiconductor (MOS) with multiple drain vias is designed with a horizontal layout, featuring conductive elements on the same surface, allowing for wafer-level chip scale packaging without traditional lead frames or wire bonding, and utilizing low-resistance copper-containing metals for connection layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a vertical design is adopted for MOS chips, then the drain region can be located below the gate and source regions, but the packaging process becomes complex and on-resistance cannot be further decreased
Solution Approach 1:
The patent inverts the traditional vertical design by placing the drain region horizontally adjacent to the gate and source regions on the same surface, rather than positioning it vertically below. This inversion eliminates the need for complex packaging processes while reducing on-resistance through shorter current paths and direct electrical connections.
Solution Approach 2:
The patent transitions from a vertical three-dimensional arrangement to a horizontal two-dimensional layout on the chip surface. By redistributing the drain, gate, and source regions horizontally, the design achieves both simplified packaging and reduced on-resistance without requiring wire bonding or lead frames.
2Ease of operation
If traditional lead frames and wire bonding are used, then electrical connections can be established, but the product size increases and impedance increases
Solution Approach 1:
The patent extracts and eliminates the traditional lead frame and wire bonding components from the electrical connection system. By integrating all electrical connections directly onto the chip surface through horizontally arranged regions, the design reduces product size and impedance while maintaining full electrical connection capability.
Solution Approach 2:
The patent merges the functions of the lead frame, wire bonding, and chip contacts into a single integrated horizontal layout. The drain, gate, and source regions are positioned adjacent to each other on the chip surface, allowing direct electrical connections without external packaging components.
Data Source
AI summary
A metal oxide semiconductor (MOS) with multiple drain vias includes a semiconductor substrate, which is divided into a gate region, a source region and a drain region. On the same surface of the semiconductor substrate in the gate region, a connection layer is formed in the source region and the drain region with a low-resistance metal material. A plurality of conductive elements, such as solder balls, can be directly arranged on the connection layer, so that the MOS can be soldered to the circuit board through the conductive elements distributed on the same surface. In the drain region, there are a plurality of vias. The inside of each via is filled with the connection layer and extends to the inside of the semiconductor substrate. With the aforementioned structure, the MOS has the advantage of low on-resistance RDS(ON).